ISE Design Suite 10.1 offers an integrated environment for FPGA logic design.
The ISE™ Design Suite 10.1 provides a powerful front-to-back design solution to help you achieve even the most aggressive design goals in less time. New features and technologies in this latest release provide easier pin-planning, faster runtimes, support for distributed processing, improved power management, and much more.
Introducing PlanAhead Lite
All ISE Design Suite configurations now include PlanAhead™ Lite, a subset of the award-winning PlanAhead Design and Analysis Tool. PlanAhead and PlanAhead Lite provide the same easy-to-use environment. PlanAhead Lite provides the I/O pin planning capabilities of the PinAhead technology. It also includes design analysis and floorplanning capabilities as well as implementation control with the ExploreAhead environment.
Download a free 60 day evaluation of of the products in the ISE Design Suite 10.1 and start your design today!
The ISE Design Suite 10.1 delivers:
Optimal Performance
Average 8% Faster Performance than the previous major release
ISE 10.1 delivers easy to use technologies to help you achieve even the most agressive performance goals in less time:
- New SmartXplorer leverages distributed processing in a Linux network to identify optimal impementation settings for a design and up to 38% additional performance
- The ISE Design Suite now includes new PlanAhead Lite offering access to many of the features available in the award winning PlanAhead Design and Analysis Tool
- Improvements in the default optimizations allowing improved placement of large blocks (e.g., DSP48 and BRAM), accuracy improvements for skew comutation, enhancements to packing and clock placer algorithms, and much more
Ultimate Productivity
The ISE Design Suite 10.1 helps you achieve design goals faster
From product installation through design verification, the ISE Design Suite 10.1 helps you make maximum use of your time and design resources:
- Average 1.8X faster implementation runtimes
- PinAhead technology in new PlanAhead Lite provides earlier FPGA to PCB I/O definition. PinAhead offers an intuitive solution to the complexities of managing the interface between an FPGA and the PCB
- Goal-based implementation allows automatic assignment of settings to deliver results specific to your design objectives (e.g., Performance, Runtime, Area, or Power)
- The ISE Design Suite reduces RTL simulation runtime by up to 2X as a result of collaboration with EDA verification partners
- Industry first IEEE encryption for Virtex-5 FPGA Hard-IP simulation models provides an average 2X faster simulation runtime compared with SmartModels
Power
Lower Dynamic Power by an Average 12%
ISE 10.1 provides the tools and technologies to help you manage power for your FPGA design with early accurate power estimation and with power optimization:
- Advanced synthesis and implementation algorithms deliver an average 12% lower dynamic power for the Spartan-3A family and 10% for Virtex-5 families
- With goal-based implementation, ISE 10.1 offers a simple, one-step process to specify power optimization
- Free, downloadable XPower Estimator spreadsheets for the leading Xilinx FPGAs lets customers quickly and easily estimate their project's power consumption with device-specific spreadsheet tools.
- XPower Analyzer included with all configuration of ISE performs detailed design-based power consumption analysis, including importing simulation files for detailed design accuracy
- Find answers to your power-related questions at Xilinx Power Solutions, www.xilinx.com/power
