PlanAhead Design Analysis Tool
PlanAhead™ delivers a faster, more efficient FPGA design solution to help achieve your performance goals.
The PlanAhead tool streamlines the design step between synthesis and place and route, allowing you to divide a larger design up into smaller, more manageable blocks and focus efforts toward optimization of each module. This methodology results in dramatically improved performance and quality of the entire design.
Introducing PlanAhead Lite
All ISE® Design Suite configurations now include PlanAhead Lite, a subset of the award-winning PlanAhead Design and Analysis Tool. PlanAhead and PlanAhead Lite tools provide the same easy-to-use environment. PlanAhead Lite provides the I/O pin planning capabilities of the PinAhead technology. It also includes design analysis and floorplanning capabilities as well as implementation control with the ExploreAhead environment.
Video Demonstrations
View these product demonstrations videos to help you get started and make the most of your PlanAhead experience:
PinAhead Technology for Easier Pin Planning
PlanAhead includes PinAhead Technology to help users better deal with the complexities of pin assignments. PinAhead offers an environment for fully automatic or semi-automated assignment of I/O ports to physical Package Pins.
ExploreAhead
ExploreAhead, integrated within PlanAhead, is an implementation exploration tool. By managing multiple implementation runs, ExploreAhead allows the user to execute multiple implementation runs based on strategies they’ve defined or predefined strategies shipped as factory defaults. In a Linux environment, ExploreAhead provides the ability to run the implementation on remote hosts.
Block-Based, Incremental Design
PlanAhead provides hierarchical, block-based, modular and incremental design methodologies, enabling designers to change only part of the design, leaving placement of the rest intact, thereby shortening design iterations. It helps you consistently maintain the required performance, even while making frequent changes.
Powerful Ease-of-Use
PlanAhead delivers an intuitive environment providing schematic, floorplan, or device views of your design. You can define and refine the hierarchy of your design for better results and more efficient use of resources to achieve optimal performance and greater utilization.
Device Family Support
- Virtex™-5 LX, LXT, SXT, FXT
- Virtex-4 FX, LX, SX
- Virtex-II Pro
- Virtex-II
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- Spartan™-3A DSP
- Spartan-3A, 3AN
- Spartan-3, 3E
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System Requirements
- Microsoft Windows XP Professional (32 and 64-bit)
- Microsoft Windows Vista Business (32 and 64-bit)
- Red Hat Enterprise Linux WS 4 (32 and 64- bit)
- Red Hat Enterprise Linux Desktop 5 (32 and 64-bit)
- SUSE Linux Enterprise 10 (32 and 64-bit)
Key Features
- Signal Integrity - PlanAhead provides functionality to check limits for Weighted Average SSO (WASSO) analysis. This allows designers to more easily limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.
- Partial Reconfiguration - PlanAhead simplifies the powerful, yet complex, design flow for partial reconfiguration. Partial reconfiguration is a unique method of changing a dynamic portion of a design while the static portion continues to operate. Partial reconfiguration allows you to reduce the size, weight, cost and power of your design. Users interested in exploring the benefits of Partial Reconfiguration are encouraged to contact their local Xilinx FAE.
- TimeAhead - TimeAhead is a flexible timing analyzer integrated into PlanAhead. It allows you to estimate route delays before running place and route. Using the PlanAhead block-based approach, the accuracy of timing estimates will improve as blocks in the design are implemented through place and route.
