Xilinx provides Web Power Tools for pre-implementation power estimates and XPower tools for post implementation power analysis. We believe that both our Web Power and XPower tools deliver results that correlate well to actual silicon measurements when used correctly. The best power estimates are those done on a completed and routed design that has been loaded into the XPower tool and stimulated with a functionally accurate set of stimulus vectors.
Xilinx Web Power Tools help estimate total power consumption accurately prior to design implementation. System architects can estimate power using high-level design details and make intelligent design choices on clock frequencies, implementing a function using hard IP or logic, type of I/O standard to use, and other factors. The Web Power Tool relies exclusively on the user’s estimates of their FPGA design parameters such as utilization, toggle rates, operating conditions, etc. This quick start guide enables users to input their design parameters correctly into the Xilinx Web Power Tool.
Important Information
Paying attention to a few simple guidelines can make the power estimates obtained from the Web Power Tool track quite closely to the actual silicon results.
Voltage Variation
- If you expect to run the design at Vccint less than the default value, enter the estimated value. Refer to the product datasheet for the allowed range. E.g., Vccint range allowed in Virtex®-4 FPGAs is 1.14V to 1.26V.
Thermal Information
- Set the ambient temperature for the device based on the type of estimate being done. A general rule of thumb for room temperature operating environment is to use an ambient temperature of 25°C. Note that even for equipment deployed at room temperature, the operating temperatures in the chassis can be higher. After entering the ambient temperature and heatsink/airflow conditions, the tool will estimate the junction temperature. For worst-case estimates, the junction temperature should not exceed 85°C for commercial devices and 100°C for industrial devices.
- Users can also manually override the junction-to-ambient thermal resistance value.
CLB Logic Power
- The number of slices entered into the tool should be entered as the number of occupied slices as stated in the ISE map report (design.mrp). If the design is not yet mapped, use 0.8 times the number of LUTs or ALUTs estimated. The LUT count used is the total of LUTs used as logic, Select RAM or Shift Registers.
- Specify the quantity of Shift Register and Select RAM LUTs used as listed in the MAP report.
- The number of flip-flops entered into the tool should be obtained from the ISE map report or user estimated.
- The toggle rate entered needs to be realistic. A good, conservative value for most large designs is 20%.
- The amount of routing used should be set to “medium” for most designs. This corresponds to an average net fanout of 2-4 loads, which we have found to be typical of most customer designs. If the customer knows the actual average fanout, the other settings could be used (“low” for average fanout <2 and “high” for average fanout >4).
Accurately specify the usage of the dedicated IP blocks
- FIFO: Enter the number of block RAMs used as FIFOs along with port widths. Note that not all Xilinx FPGAs have built-in logic to configure a Block RAM as a FIFO.
- Block RAM: Accurately specify the width and depth as well as read and write percentages for block RAMs.
- DSP48: Specify the number of DSP48s. At architecture level, it is good to assume that each DSP48 is equivalent to a MAC. Use the multiplier register (MREG) which is a pipelining register in the data path that helps increase performance and reduce power. Choose low toggle rate for the DSP48.
- DCM: Use the correct frequency mode: In most cases, “high” will be used if the input clock frequency is 150MHz or above, and “low” will be used if the input clock frequency is below 150MHz.
- Input/Output: Choose the correct I/O Standard with the correct drive strength. Options with “DCI” in the text correspond to on-chip dynamically controlled impedance. When using DCI, you move the power consumption from outside the device into the device. Pay careful attention to IOB toggle rates and output enable rate. In most cases the output enable signal is not toggled at high rates, Choose single data rate (SDR) or double data rate (DDR) for the IOB registers depending on the standard. Group the I/Os with similar toggle rates and SDR/DDR options together