BSDL Files

High Quality Testing Models

Xilinx BSDL files are available for every part and package combination of IEEE 1149.1 compatible devices. These files can be used by third party boundary scan tool vendors to generate test vectors and perform tests. BSDL files are also used by Xilinx programming software when configuring devices through Boundary Scan.

Third Party Validation

To reduce risk and raise confidence in testing and programming operations, Xilinx BSDL files are validated by JTAG Technologies. This service confirms BSDL files accurately describe boundary-scan features of the device. Syntax and semantic checks are included to confirm the BSDL file conforms to IEEE standard 1149.1.

To validate, every I/O pin within a sample device is connected to the boundary-scan tool. Appropriate power and grounds are connected, and compliance enable pins described in the BSDL file are set to enable boundary-scan. The BSDL file is used as an input to the ScanWorks test development process where the BSDL file information drives test vector generation. Standard ScanWorks tools are used to generate the following tests:

Scan path verification tests validate:

• Basic TAP controller operation, including PAUSE state operation
• BYPASS register length and capture value
• Instruction register length and capture value
• Instruction register opcode definitions
• IDCODE register length and capture value
• USERCODE register length and capture value (if any is specified)
• Boundary register length
• Test Logic Reset operation, both hard and soft
  

Interconnect tests demonstrate:

• Logic one and a logic zeros can be driven by each boundary-scan output pin
• All output pins can be disabled by the specified control cells
• Logic one and a logic zeros can be received by each boundary-scan input pin
• All bi-directional pins can be configured as either an input or an output
• All boundary register bits are connected to the specified IO pin or control cell