Step 5: Mapping the Design

At this point, the input netlist is being translated (once again), and merged into a single design file. Furthermore, the design will be mapped into CLBs and IOBs. After mapping, the design will be placed and routed. The final step in the design flow is the Configure step in which a configuration bitstream is created for downloading to a target device or for formatting into a PROM programming file.

Map performs the following functions:

• Allocates CLB and IOB resources for all basic logic elements in the design
  
  
• Processes all location and timing constraints, performs target device optimizations, and runs a design rule check on the resulting mapped netlist.
  
  

After the MAP step is done, the Flow Engine shuts down and the Implement Status dialog box appears, as shown in the following figure.

Figure 2.12 Implement Status Dialog Box

The following steps show you how to use the report browser.

1. Select Reports to invoke the Report Browser window. The Translation Report appears as the first report generated. The Map Report and Logic Level Timing Report files are created as a result of the Map stage completing. New reports that have not been read are denoted with a gold star in the upper left corner of the file icon, as shown in the following figure.
   
   

   Figure 2.13 Report Browser after Running Map

2. Double-click on a report to review its output. The following table lists the types of reports and describes their contents.
   
   The following table lists the types of reports available to you.
   
   

   Table 2_2 Report Browser Reports

   Report	Description
   Translation Report	Includes warning and error messages from the translation process.
   Map Report	Includes information on how the target device resources are allocated, references to trimmed logic, and device utilization. For detailed information on the Map report, refer to the Development System Reference Guide.
   Logic Level Timing Report	Provides a summary analysis of your timing constraints based on block delays and estimates of route delays. This report is produced after Map and prior to PAR (Place And Route).

   
   
   
   
3. Select OK to close the Implement Status dialog. Keep the Report Browser open for now. We will be evaluating some of these reports in further detail in the next section.
   
   

Notice that the Design Manager project view displays the status of the revision as (Mapped, OK). “Mapped” refers to the state of the design and is updated throughout the tutorial as the different compilation stages are completed. “OK” refers to the status of the current state and indicates no errors in the design processing.

The design has now been mapped to the target architecture. The next step involves checking the design paths for block delays.