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This appendix supplies examples for JTAG programming, including the following:
The following example outlines instantiating the BSCAN symbol for XC5200 devices:
entity example is
port (a, b, c: in bit; d: out bit);
end example;
architecture xilinx of example is
component bscan
port(tdi, tms, tck: in bit; tdo: out bit);
end component;
component tck
port ( i : out bit );
end component;
component tdi
port ( i : out bit );
end component;
component tms
port ( i : out bit );
end component;
component tdo
port ( o : in bit );
end component;
component ibuf
port (i: in bit; o: out bit);
end component;
component obuf
port(i: in bit; o: out bit);
end component;
signal tck_net, tck_net_in : bit;
signal tdi_net, tdi_net_in : bit;
signal tms_net, tms_net_in : bit;
signal tdo_net, tdo_net_out : bit;
begin
u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net,
tdo=>tdo_net_out);
u2: ibuf port map(i=>tck_net_in, o=>tck_net);
u3: ibuf port map(i=>tdi_net_in, o=>tdi_net);
u4: ibuf port map(i=>tms_net_in, o=>tms_net);
u5: obuf port map(i=>tdo_net_out, o=>tdo_net);
u6: tck port map (i=>tck_net_in);
u7: tdi port map (i=>tdi_net_in);
u8: tms port map (i=>tms_net_in);
u9: tdo port map (o=>tdo_net);
process(c)
begin
if(c'event and c='1') then
d <= a;
end if;
end process;
end xilinx;
The following example outlines instantiation of the BSCAN symbol for XC4000 devices:
entity example is
port (a, b, c: in bit; d: out bit);
end example;
architecture xilinx of example is
component bscan
port(tdi, tms, tck: in bit; tdo: out bit);
end component;
component tck
port ( i : out bit );
end component;
component tdi
port ( i : out bit );
end component;
component tms
port ( i : out bit );
end component;
component tdo
port ( o : in bit );
end component;
signal tck_net : bit;
signal tdi_net : bit;
signal tms_net : bit;
signal tdo_net : bit;
begin
u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net,
tdo=>tdo_net);
u2: tck port map (i=>tck_net);
u3: tdi port map (i=>tdi_net);
u4: tms port map (i=>tms_net);
u5: tdo port map (o=>tdo_net);
process(c)
begin
if(c'event and c='1') then
d <= a;
end if;
end process;
end xilinx;
// XC5200 - Boundary SCAN Verilog code
module bnd_scan (a, b, c, d);
input a, b, c;
output d;
reg d;
wire TCK_P, TDI_P, TMS_P, TDO_P;
BSCAN U0 (.TDO (TDO_P), .TDI (TDI_P), .TMS (TMS_P), .TCK (TCK_P));
TDI U1 (.i (TDI_P));
TCK U2 (.i (TCK_P));
TMS U3 (.i (TMS_P));
TDO U4 (.o (TDO_P));
always@ (posedge c)
d<=a;
endmodule
module TDI(i) /* synthesis black_box */;
output i /* synthesis .ispad=1 */;
endmodule
module TCK(i) /*synthesis black_box*/;
output i /*synthesis .ispad=1*/;
endmodule
module TMS(i) /*synthesis black_box*/;
output i /*synthesis .ispad=1*/;
endmodule
module TDO(o) /*synthesis black_box .noprune=1 */;
input o /*synthesis .ispad=1*/;
endmodule
module BSCAN(TDO, TCK, TDI, TMS) /* synthesis black_box */;
output TDO;
input TCK, TDI, TMS;
endmodule
#-- TCL Script
#device options
set_option -technology XC5200
set_option -part XC5202
set_option -package PC84
set_option -speed_grade -3
#add_file options
add_file -verilog "bnd_scan.v"
#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler true
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true
#set result format/file last
project -result_file "bnd_scan.xnf"
project -run
#end TCL
You can instantiate a BSCAN cell by using the import library supplied with Synplify. The Synplify Xilinx Macro Libraries contain pre-defined black-boxes for the Xilinx macros so that you can manually instantiate them into your design.
For VHDL based designs all one has to do is add the following 2 lines in the VHDL and instantiate the BSCAN component. Please look in the $SYNPLCTY\lib\xilinxf000.vhd for BSCAN component and its port interface list. For xc5200 VHDL designs, use xc4000.vhd "black box" instantiation as an example.
library xc4000;
use xc4000.components.all;
For Verilog designs, just add the xc4000.v file in the source file list along with the source design file. The xc4000.v file is also in the $SYNPLCTY\lib\xilinx directory. For xc5200 Verilog designs, use xc4000.v black box instantiation as an example.
Note: You must instantiate the complete set of Xilinx boundary scan modules (bscan,tdi,tck,tms,tdo) in to your design.
// XC4000e/ex/xl - Boundary SCAN Verilog code
module bnd_scan (a, b, c, d);
input a, b, c;
output d;
reg d;
wire TCK_P, TDI_P, TMS_P, TDO_P;
BSCAN U1 (.TDO (TDO_P), .TDI (TDI_P), .TMS (TMS_P), .TCK (TCK_P),
.DRCK (open), .IDLE (open), .SEL1 (open), .SEL2 (open),
.TDO1 (1'b0), .TDO2 (1'b0));
TDI U2 (.i (TDI_P));
TCK U3 (.i (TCK_P));
TMS U4 (.i (TMS_P));
TDO U5 (.o (TDO_P));
always@ (posedge c)
d<=a;
endmodule
#-- TCL scipt
#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1
#add_file options
add_file -verilog "/products/synplify.ver3_0/lib/xilinx/xc4000.v"
add_file -verilog "bnd_scan.v"
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true
#set result format/file last
project -result_file "bnd_scan.xnf"
project -run
#end TCL
-- XC4000e/ex/xl - Boundary SCAN VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;
entity bnd_scan is
port (
a, b, c: in bit;
d: out bit
);
end bnd_scan;
architecture xilinx of bnd_scan is
signal TCK_P : STD_LOGIC;
signal TDI_P : STD_LOGIC;
signal TMS_P : STD_LOGIC;
signal TDO_P : STD_LOGIC;
begin
U0: BSCAN port map (TDO => TDO_P,
TDI => TDI_P,
TMS => TMS_P,
TCK => TCK_P,
DRCK => open,
IDLE => open,
SEL1 => open,
SEL2 => open,
TDO1 => '0',
TDO2 => '0');
U1: TDI port map (I =>TDI_P);
U2: TCK port map (I =>TCK_P);
U3: TMS port map (I =>TMS_P);
U4: TDO port map (O =>TDO_P);
process (c)
begin if (c'event and c='1')
then d <= a;
end if;
end process;
end xilinx;
#-- TCL script
#device options
set_option -technology XC4000E
set_option -part XC4003E
set_option -package PC84
set_option -speed_grade -1
#add_file options
add_file -vhdl -lib work "bnd_scan.vhd"
add_file -_include "/products/synplify.ver3_0/lib/xilinx/xc4000.vhd"
#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true
#set result format/file last
project -result_file "bnd_scan.xnf"
project -run
#end TCL
Note: If you experience problems instatiating, the simplest workaround for you would be to replace the VHDL "open" statements with actual signal names. All you have to do is declare 4 signals of type std_logic and connect the DRCK, IDLE, SEL1 and SEL2 ports of BSCAN to these signals.
Another solution that would work requires a change in the BSCAN component declaration in the xc4000.vhd file located in your SYNPLCTY\LIB\xilinx directory.
Please change the BSCAN component to be component BSCAN
port(
TDO : out STD_LOGIC ;
DRCK : out STD_LOGIC ;
IDLE : out STD_LOGIC ;
SEL1 : out STD_LOGIC ;
SEL2 : out STD_LOGIC ;
TDI : in STD_LOGIC;
TMS : in STD_LOGIC;
TCK : in STD_LOGIC;
TDO1 : in STD_LOGIC;
TDO2 : in STD_LOGIC);
end component;
Notice that the initialization for the output ports have been removed.
-- XC5200 - Boundary Scan VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
entity bnd_scan is
port (a, b, c: in bit;
d: out bit);
end bnd_scan;
architecture xilinx of bnd_scan is
attribute black_box : boolean;
attribute black_box_pad_pin : string;
attribute synthesis_noprune : boolean;
component BSCAN
port (TDI, TMS, TCK : in STD_LOGIC;
TDO : out STD_LOGIC);
end component;
attribute black_box of BSCAN : component is true;
component TDI
port (I : out STD_LOGIC);
end component;
attribute black_box_pad_pin of TDI : component is "I";
component TCK
port (I : out STD_LOGIC);
end component;
attribute black_box_pad_pin of TCK : component is "I";
component TMS
port (I : out STD_LOGIC);
end component;
attribute black_box_pad_pin of TMS : component is "I";
component TDO
port (O : in STD_LOGIC);
end component;
attribute black_box_pad_pin of TDO : component is "O";
attribute synthesis_noprune of TDO : component is true;
signal TCK_P : STD_LOGIC;
signal TDI_P : STD_LOGIC;
signal TMS_P : STD_LOGIC;
signal TDO_P : STD_LOGIC;
begin
U0: BSCAN port map (TDO => TDO_P,
TDI => TDI_P,
TMS => TMS_P,
TCK => TCK_P);
U1: TDI port map (I =>TDI_P);
U2: TCK port map (I =>TCK_P);
U3: TMS port map (I =>TMS_P);
U4: TDO port map (O =>TDO_P);
process (c)
begin
if (c'event and c='1') then
d <= a;
end if;
end process;
end xilinx;
#-- TCL Script
#device options
set_option -technology XC5200
set_option -part XC5202
set_option -package PC84
set_option -speed_grade -3
#add_file options
add_file -vhdl -lib work "bnd_scan.vhd"
#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler false
#map options
set_option -frequency 0.000
set_option -fanout_limit 100
set_option -force_gsr true
set_option -disable_io_insertion false
set_option -xilinx_m1 true
#set result format/file last
project -result_file "bnd_scan.xnf"
project -run
#end TCL
VHDL Code for Instantiating BSCAN in the XC5200:
-- XC5200 example of instantiating the BSCAN symbol
entity example is
port (a, b, c: in bit; d: out bit);
end example;
architecture xilinx of example is
component bscan
port(tdi, tms, tck: in bit; tdo: out bit);
end component;
component tck
port ( i : out bit );
end component;
component tdi
port ( i : out bit );
end component;
component tms
port ( i : out bit );
end component;
component tdo
port ( o : in bit );
end component;
component ibuf
port (i: in bit; o: out bit);
end component;
component obuf
port(i: in bit; o: out bit);
end component;
signal tck_net, tck_net_in : bit;
signal tdi_net, tdi_net_in : bit;
signal tms_net, tms_net_in : bit;
signal tdo_net, tdo_net_out : bit;
begin
u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net,
tdo=>tdo_net_out);
u2: ibuf port map(i=>tck_net_in, o=>tck_net);
u3: ibuf port map(i=>tdi_net_in, o=>tdi_net);
u4: ibuf port map(i=>tms_net_in, o=>tms_net);
u5: obuf port map(i=>tdo_net_out, o=>tdo_net);
u6: tck port map (i=>tck_net_in);
u7: tdi port map (i=>tdi_net_in);
u8: tms port map (i=>tms_net_in);
u9: tdo port map (o=>tdo_net);
process(c)
begin
if(c'event and c='1') then
d<= a;
end if;
end process;
end xilinx;
Runscript for compiling XC5200 BSCAN VHDL Example:
PART = 5202PC84-5
TOP = example
analyze -format vhdl "bscan5k.vhd"
elaborate TOP
set_port_is_pad "*"
insert_pads
set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5
set_dont_touch u6
set_dont_touch u7
set_dont_touch u8
set_dont_touch u9
compile
set_attribute TOP "part" -type string PART
write -f xnf -h -o "bscan5k.sxnf"
Verilog Code for Instantiating BSCAN in the XC4000
Note: VERILOG IS CASE SENSITIVE! BE SURE TO FOLLOW THE CASE USED IN THIS EXAMPLE!
//XC4000/XC4000E Example of instantiating BSCAN symbol
module example (a,b,c,d);
input a, b, c;
output d;
reg d;
wire tck_net;
wire tdi_net;
wire tms_net;
wire tdo_net;
BSCAN u1 (.TDI(tdi_net), .TMS(tms_net), .TCK(tck_net), .TDO(tdo_net));
TDI u2 (.I(tdi_net));
TMS u3 (.I(tms_net));
TCK u4 (.I(tck_net));
TDO u5 (.O(tdo_net));
always@(posedge c)
d<=a;
endmodule
Runscript for compiling XC4000 BSCAN Verilog Example:
PART = 4025ehq240-3
TOP = example
read -format verilog "bscan4k.v"
set_port_is_pad "*"
insert_pads
set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5
compile
replace_fpga
set_attribute TOP "part" -type string PART
write -f xnf -h -o "bscan4k.sxnf"
Verilog Code for Instantiating BSCAN in the XC5200:
//XC5200 Example of instantiating BSCAN symbol
module example (a,b,c,d);
input a, b, c;
output d;
reg d;
wire tck_net, tck_net_in;
wire tdi_net, tdi_net_in;
wire tms_net, tms_net_in;
wire tdo_net, tdo_net_out;
BSCAN u1 (.TDI(tdi_net), .TMS(tms_net), .TCK(tck_net), .TDO(tdo_net));
TDI u2 (.I(tdi_net_in));
TMS u3 (.I(tms_net_in));
TCK u4 (.I(tck_net_in));
TDO u5 (.O(tdo_net_out));
IBUF u6 (.I(tdi_net_in), .O(tdi_net));
IBUF u7 (.I(tms_net_in), .O(tms_net));
IBUF u8 (.I(tck_net_in), .O(tck_net));
OBUF u9 (.I(tdo_net), .O(tdo_net_out));
always@(posedge c)
d<=a;
endmodule
Runscript for compiling XC5200 BSCAN Verilog Example:
PART = 5202PC84-5
TOP = example
read -format verilog "bscan5k.v"
set_port_is_pad "*"
insert_pads
set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5
set_dont_touch u6
set_dont_touch u7
set_dont_touch u8
set_dont_touch u9
compile
set_attribute TOP "part" -type string PART
write -f xnf -h -o "bscan5k.sxnf"
VHDL Code for Instantiating BSCAN in the XC4000:
-- XC4000/XC4000E example of instantiating the BSCAN symbol
entity example is
port (a, b, c: in bit; d: out bit);
end example;
architecture xilinx of example is
component bscan
port(tdi, tms, tck: in bit; tdo: out bit);
end component;
component tck
port ( i : out bit );
end component;
component tdi
port ( i : out bit );
end component;
component tms
port ( i : out bit );
end component;
component tdo
port ( o : in bit );
end component;
signal tck_net : bit;
signal tdi_net : bit;
signal tms_net : bit;
signal tdo_net : bit;
begin
u1: bscan port map (tdi=>tdi_net, tms=>tms_net, tck=>tck_net,
tdo=>tdo_net);
u2: tck port map (i=>tck_net);
u3: tdi port map (i=>tdi_net);
u4: tms port map (i=>tms_net);
u5: tdo port map (o=>tdo_net);
process(c)
begin
if(c'event and c='1') then
d<= a;
end if;
end process;
end xilinx;
Runscript for compiling XC4000 BSCAN VHDL Example:
PART = 4025EHQ240-3
TOP = example
analyze -format vhdl "bscan4k.vhd"
elaborate TOP
set_dont_touch u1
set_dont_touch u2
set_dont_touch u3
set_dont_touch u4
set_dont_touch u5
set_port_is_pad "*"
insert_pads
compile
replace_fpga
set_attribute TOP "part" -type string PART
write -f xnf -h -o "bscan4k.sxnf"
Note: set_dont_touch/dont_touch are case-sensitive with respect to instance names.