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There are two preferences available that you may want to select before initiating a session. They are Concurrent Mode and Use HIGHZ instead of BYPASS. These options are selected as follows:
File
Preferences
The Preferences dialog box will appear.
The JTAG Programmer normally uses a sequential methodology when accessing Xilinx CPLDs for ISP operations. It selects a device to program and sets all other devices in the boundary-scan chain into BYPASS mode. Concurrent Mode erases, programs and verifies selected devices in the chain without placing these parts in BYPASS mode. This has the advantage of saving time by executing operations simultaneously.
For example, it takes few seconds to completely erase all the sectors of a device. If you have several devices in a chain, these erase times can add up. In concurrent mode the erasures can take place simultaneously, saving time.
Concurrent mode is applicable only to Xilinx CPLD devices. Since Xilinx FPGA devices are SRAM based; their access method precludes this kind of operation.
The JTAG Programmer usually places parts in BYPASS mode when other devices in the boundary-scan chain are being programmed. This option places XC9500/XL/XV, Spartan-II and Virtex devices in high impedance mode instead. If you suspect that noise is degrading the integrity of ISP operations, use this mode to reduce the signal activity level in the system.
If you decide to use HIGHZ instead of BYPASS you must be certain that your design can tolerate XC9500/XL/XV or Virtex device pins floating. If these pins connect to memory enable pins, for instance, their floating values may inadvertently cause the devices to turn on, potentially damaging their drivers or parts downstream from them.
If your boundary-scan chain consists of all Xilinx devices (FPGA, CPLD and SPROM), then you can select all devices at once.
Use Edit
Select All, or highlight each device individually, then:Operations
Program
The program options box appears. Select the desired programming options, then click OK.
When the programming operation is complete, the programming status of each Xilinx programmable device is reported as shown:
There are two ways to set up the chain for JTAG Programmer operations. The first is to highlight a part and select an operation for it using the Operations menu. You select an operation from the menu, then highlight the next part and select an operation for it, or you may highlight all parts and select an operation for all parts.
The other way is to use the Chain Operations dialog box. This presents you with a "spreadsheet" approach to boundary-scan chain. This method allows you select and execute operations for all the parts in the chain, all from the same dialog box. To access this dialog box:
Operations
Chain Operations...
The dialog box appears. In the Operations column you may change the operation of any part by clicking once on the current device to highlight it, then clicking once on the down arrow adjacent to Selected Device Operation. This will produce a pull-down menu showing the operations you can set for that part.
Bypass is the only supported mode of Operation for non-Xilinx parts. These parts will appear under Device Type. Note that Bypass is selected as the default Operation of each foreign part.
Select the Execute button. Download will begin.
In either operation mode a pop-up menu appears and delivers processing messages. When processing has completed, a message log is available to examine the results of the execution.
The Edit menu provides easy means for inserting and deleting parts from a chain, as well as the means to assign a new JEDEC file to a part.
To insert a device into the chain, use the Add Device command. First make sure that the prompt is at the location in the chain where you want to insert the device. If it is not, use either the mouse or the arrow keys to move it. Then insert the device as follows:
Edit
Add Device
To change the jedec file associated with a device in the chain, highlight the device and select:
Edit
Properties
Use the browse key to select another jedec file or simply enter the path and filename of the file. The program will associate the new file with the device.
Each jedec assigns a device type to the device in the chain. If the jedec file was not created for the actual device you have on your board, an error will result when you attempt to program the device.
For an 1800 prom, clicking OK on the properties dialog displays a list of 1800 parts which can fit the specified prom file. Select the desired part name and click OK.
To delete an entry in the device chain, use the Cut command. All devices move up one entry in the chain.
Edit
Cut
To select the entire chain for an operation, use
Edit
Select All
To unselect the chain:
Edit
Unselect All
When operating in SVF mode, chain modifications are not allowed so as to ensure that the resulting SVF is self-consistent.
To save a JTAG Programmer chain description for later use, create a Chain Description File (.cdf) using:
File
Save
If the chain has not been previously saved, the Save As dialog box will appear. This screen will allow you to select a directory and path to place the file in. You can also name the file, but you should retain the .cdf file extension. If you wish to save your file under another name than already selected, use:
File
Save As...
To name your file, use the mouse to highlight Untitled or the old file name on the File Name line, then type in the name you want and click once on OK.

Saving a File
The debugger provides you with a method to apply boundary-scan test access port stimulus. This feature allows you to set TDI and TMS, then pulse TCK a specified number times. You can monitor TDO, TDI and TMS using an oscilloscope or logic probe to see if the boundary-scan chain is operating correctly. The debugger also displays the current TAP state and allows you to reset the chain to Run Test Idle.
To access the debugger:
File
Debug Chain
The Boundary-Scan Chain Debug dialog box appears as shown in Figure 3-13.
The features of this dialog box operate as follows:
The first selection box allows you to set a logic state for TDI. This state will not be set until you click on the Apply button.
The second selection box allows you to set a logic state for TMS. This state will not be set until you click on the Apply button.
The third selection box allows you to set a number of pulses to apply to TCK. These pulses will not be sent until you click on the Apply button. If you want to see the pulses again, click the Apply button as often as you want.
The TAP State window displays the current state of the controller.
The Return to RTI (Run Test Idle) button executes a Test Logic Reset, then returns to Run Test Idle.
Any Xilinx CPLD device selected for programming can be secured with the Write Protect or Read Protect or both.
When enabled, Read Protect disables reading the programmed contents of a device (the Device ID and usercode/signature and boundary scan register remain readable).
Write Protect allows only the reading of the programmed data. The device contents cannot be altered or re-programmed.
When both Read Protect and Write Protect are enabled, the device can be neither read nor re-programmed.
To enable either security function simply place a check in the corresponding box when programming the device.
Data security operations can be overridden only by erasing the device. For Read Protection override, you simply erase the part. For Write Protection override, you must select the override write protect option from the Erase Options dialog box.
Parallel load: This option is used to determine if the prom is to be read out serially or in parallel on D0-D7 data lines. By default, the prom is configured to be read out serially. By selecting the parallel load option, the prom can be programmed to output data on lines D0-D7 to be used to configure a Virtex device in the Select-map mode, or a Spartan device in Express mode.
Load FPGA: By selecting this option the prom will automatically start FPGA configuration at the end of programming (if the programming is successful). This option sets the CF low for 300 ns, which in turn causes the prog to be pulled low (on the FPGA) which initiates configuration of the FPGA. This mechanism will only work if the prom and the FPGA are connected as required for configuration purposes.
Skip User Array: This option gives you the flexibility to alter miscellaneous bits (security, load FPGA, Select Map) without affecting the contents of the user array. This makes it possible to set these options after programming the user array. Note that because these parts are Flash based, if you program these bits, you cannot reverse these bits without erasing the entire array (consistent with the behavior of the security option).