Simulating Verilog

Defining Global Signals in Verilog

To specify the global set/reset or global reset, you must first define them in the $XILINX/verilog/src/glbl.v module. The VHDL UniSims library contains the ROC, ROCBUF, TOC, TOCBUF, and STARTBUF cells to assist in VITAL VHDL simulation of the global set/reset and tristate signals. However, Verilog allows a global signal to be modeled as a wire in a global module, and, thus, does not contain these cells.

Using the glbl.v Module

The glbl.v module connects the global signals to the design, which is why it is necessary to compile this module with the other design files and load it along with the design.v file and the testfixture.v file for simulation.

The following is the definition of the glbl.v file.

`timescale 1 ns / 1 ps
module glbl();
wire GR;
wire GSR;
wire GTS;
wire PRLD;
endmodule

Defining GSR/GTS in a Test Bench

There are two cases to consider when defining a GSR or GTS in a test bench: designs without a STARTUP block and designs with a STARTUP block.

Note The terms "test bench" and "test fixture" are used synonymously throughout this manual.

Designs Without a Startup Block

When you use the UniSim libraries for RTL simulation, you must set the value of the appropriate Verilog global signals (glbl.GSR or glbl.GTS) to the name of the GSR or GTS net, qualified by the appropriate scope identifiers.

The global set/reset net is present in your implemented design even if you do not instantiate the STARTUP block in your design. The function of STARTUP is to give you the option to control the global reset net from an external pin. The following example should be added to your design code and test fixture to set the GSR and GTS pin for XC4000XLA, Spartan/XL, or Virtex devices:

reg GSR;
assign glbl.GSR = GSR;
reg GTS;
assign glbl.GTS = GTS;
initial begin
GSR = 1; GTS = 1;
#100 GSR = 0; GTS = 0;
end

Example 1: No STARTUP With GSR Defined

The following design shows how to drive the GSR signal in a testfixture file at the beginning of a pre-NGDBuild Unified Library functional simulation.

In the design code, declare the GSR as a Verilog wire. The GSR will not be specified in the port list for the module. Describe the GSR to reset or set every inferred register or latch in your design. GSR does not need to be connected to any instantiated registers or latches, as shown in the following example.

module my_counter (CLK, D, Q, COUT);
input CLK, D;
output Q;
output [3:0] COUT;

wire GSR;
reg [3:0] COUT;

always @(posedge GSR or posedge CLK)
  begin
    if (GSR == 1'b1)
      COUT = 4'h0;
    else
      COUT = COUT + 1'b1;
  end
// GSR is modeled as a wire within a global module.
// So,CLR does not need to be connected to GSR and
// the flop will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
endmodule

Since the GSR is declared as a floating wire and is not in the port list, the synthesis tool optimizes the GSR signal out of the design. GSR is replaced later by the implementation software for all post-implementation simulation netlists.

In the test fixture file, set GSR to test.uut.GSR (the name of the global set/reset signal, qualified by the name of the design instantiation instance name and the test fixture instance name). Since there is no STARTUP block, a connection to GSR is made in the testfixture via an assign statement. See the following example:

`timescale 1 ns / 1 ps
module test;
reg CLK, D;
wire Q;
wire [3:0] COUT;
reg GSR;
assign glbl.GSR = GSR;
assign test.uut.GSR = GSR;
my_counter uut (.CLK (CLK), .D (D), .Q (Q), .COUT (COUT));
initial begin
  $timeformat(-9,1,"ns",12);
  $display("\t   T C G D Q C");
  $display("\t   i L S     O");
  $display("\t   m K R     U");
  $display("\t   e         T");
  $monitor("%t %b %b %b %b %h", $time, CLK, GSR, D, Q, COUT);
end
initial begin
    CLK = 0;
    forever #25 CLK = ~CLK;
end
initial begin
    #0 {GSR, D} = 2'b11;
    #100 {GSR, D} = 2'b10;
    #100 {GSR, D} = 2'b00;
    #100 {GSR, D} = 2'b01;
    #100 $finish;
end
endmodule

Designs with a STARTUP Block

For RTL simulation using the UniSim libraries, asserting global set/reset and global tri-state when the STARTUP block is specified in the design is similar to asserting global set/reset and global tristate without a STARTUP block in the design. See the "User-Controlled GSR" figure.

Figure 6-7  User-Controlled GSR

To set the GSR pin to set an external input port, the testfixture would be written as the following:

reg MYGSR;
initial begin
MYGSR = 1;
#100 MYGSR = 0;
end

You must omit the assign statement for the global signal. This is because a the global signal, glbl.GSR, is defined within the STARTUP block to make the connection between the user logic and the global GSR net embedded in the UniSim models for RTL simulation. For post-NGDBuild, GSR is connected in the netlist created by NGD2VER. Retaining the assign definition causes a possible conflict with these connections.

Example 1: STARTUP with GSR Pin Connector

In the following Verilog code, GSR is listed as a top-level port. Synthesis sees a connection of GSR to the STARTUP and as well to the behaviorally described counter. Although this is correct in the hardware, it is actually an implicit connection, and GSR is only listed as a connection to the STARTUP in the implementation netlist.

module my_counter (MYGSR, CLK, D, Q, COUT);
input MYGSR, CLK, D;
output Q;
output [3:0] COUT;

reg [3:0] COUT;

always @(posedge MYGSR or posedge CLK)
  begin
    if (MYGSR == 1'b1)
      COUT = 4'h0;
  else
    COUT = COUT + 1'b1;
  end
// GSR is modeled as a wire within a global module. So,
// CLR does not need to be connected to GSR and the flop
// will still be reset with GSR.
FDCE U0 (.Q (Q), .D (D), .C (CLK), .CE (1'b1), .CLR (1'b0));
STARTUP U1 (.GSR (MYGSR), .GTS (1'b0), .CLK (1'b0));
endmodule

The following is an example of controlling the global set/reset signal by driving the external MYGSR input port in a test fixture file at the beginning of an RTL or post-synthesis functional simulation when there is a STARTUP block.

The global set/reset control signal should be toggled High, then Low in an initial block.

reg MYGSR;
initial begin
MYGSR = 1; // To reset/set the device
#100 MYGSR = 0; // To deactivate GSR
end

In addition, the global signal, glbl.GSR, is defined within the STARTUP block to make the connection between the user logic and the global GSR net embedded in the UniSim models for RTL simulation. For post-NGDBuild functional simulation, post-Map timing simulation, and post-route timing simulation, GSR is connected in the Verilog netlist that is created by NGD2VER.

Example 2: STARTUP with GTS Pin Connected

In the following figure, MYGTS is an external user signal that controls GTS.

Figure 6-8  User-Controlled GTS

The following is an example of controlling the global tristate signal by driving the external MYGTS input port in a test fixture file at the beginning of an RTL or post-synthesis functional simulation when there is a STARTUP block. The global GTS model in the UniSim simulation models for output buffers (OBUF, OBUFT, and so on).

The global tristate control signal should be toggled High, then Low in an initial block.

reg MYGTS;


initial begin
MYGTS = 1; // To tristate the device;
#100 MYGTS = 0; // To deactivate GTS
end

Example 3: STARTUP with GTS Pin Not Connected

A Verilog global signal called glbl.GTS is defined within the STARTUP/STARTUP_VIRTEX block to make the connection between the user logic and the global GTS net embedded in the Unified models. For post-NGDBuild functional simulation, post-map timing simulation, and post-route timing simulation, glbl.GTS is defined in the Verilog netlist that is created by NGD2VER.

reg GTS;
assign glbl.GTS = GTS;

initial begin
GTS = 1; // To tristate the device;
#100 GTS = 0;  // To deactivate GTS
end

Simulating Special Components in Verilog

The following section provides a description and examples of simulating special components for Virtex.

Boundary Scan and Readback

The Boundary Scan and Readback circuitry can not be simulated at this time. Efforts are being made to create models for these components and should be available in the near future.

Differential I/O (LVDS, LVPECL)

The inputs of the differential pair are currently modeled with only the positive side. Whereas, the outputs have both pairs, positive and negative. For details, please see http://support.xilinx.com/techdocs/8187.htm.

The following is an example of Differential I/O.

module lvds_ex (data, data_op, data_on);
input data;
output data_op, data_on;

// Input side
IBUF_LVDS I0 (.I (data), .O (data_int));

// Output side
OBUF_LVDS OP0 (.I (data_int), .O (data_op));
wire data_n_int = ~data_int;
OBUF_LVDS ON0 (.I (data_n_int), .O (data_on));

endmodule

LUT

For simulation, the INIT attribute passed by the defparam statement is used to initialize contents of the LUT.

The following is an example of the defparam statement being used to initialize the contents of a LUT.

module lut_ex (LUT1_OUT, LUT1_IN);
input  [1:0] LUT1_IN;
output [1:0] LUT1_OUT;

// For RTL simulation only.
// The defparam will not synthesize.

// synopsys translate_off
defparam U0.INIT = 2'b01;
defparam U1.INIT = 2'b10;
// synopsys translate_on

// LUT1 used as an inverter
LUT1 U0 (.O (LUT1_OUT[0]), .I0 (LUT1_IN[0]));

// LUT1 used as a buffer
LUT1 U1 (.O (LUT1_OUT[1]), .I0 (LUT1_IN[1]));

endmodule

However, passing the INIT attribute in this manner does not initialize the contents for synthesis. All synthesis tools have their own mechanism for passing attributes to the implementation netlist. For referneces on today's popular synthesis tools, refer to the LUT Instantiation and Initialization for Synthesis table.

Table 6-11  LUT Instantiation and Initialization for Synthesis

SRL16

For simulation, the INIT attribute passed by the defparam statement is used to initialize contents of the SRL16.

The following is an example of the defparam statement being used to initialize the contents of a SRL16.

module srl16_ex (CLK, DIN, QOUT);
input CLK, DIN;
output QOUT;

// For RTL simulation only.
// The defparam will not synthesize.

// synopsys translate_off
defparam U0.INIT = 16'hAAAA;
// synopsys translate_on

// Static length - 16-bit SRL
SRL16 U0 (.D (DIN), .Q (QOUT), .CLK (CLK),
  .A0 (1'b1), .A1 (1'b1), .A2 (1'b1), .A3 (1'b1));
endmodule

However, passing the INIT attribute in this manner does not initialize the contents for synthesis. Please refer to your synthesis vendor's documentation since all synthesis tools have their own mechanism for passing attributes to the implementation netlist.

BlockRAM

For simulation, the INIT_0x attributes passed by the defparam statement are used to initialize contents of the BlockRAM.

module bram512x4 (CLK, DATA_BUSA, ADDRA, WEA, DATA_BUSB, ADDRB, WEB);
input [9:0] ADDRA, ADDRB;
input CLK, WEA, WEB;
inout [3:0] DATA_BUSA, DATA_BUSB;

wire [3:0] DOA, DOB;

assign DATA_BUSA = !WEA ? DOA : 4'hz;
assign DATA_BUSB = !WEB ? DOB : 4'hz;

// For RTL simulation only. The defparam will not synthesize.

// synopsys translate_off
defparam
U0.INIT_00 = 256'h5555aaaa5555aaaa5555aaaa5555aaaa5555aaaa,
U0.INIT_01 = 256'h5555aaaa5555aaaa5555aaaa5555aaaa5555aaaa;
// synopsys translate_on

RAMB4_S4_S4 U0 (.DOA (DOA), .DOB (DOB),
  .ADDRA (ADDRA), .DIA (DATA_BUSA), .ENA (1'b1),
  .CLKA (CLK), .WEA (WEA), .RSTA (1'b0),
  .ADDRB (ADDRB), .DIB (DATA_BUSB), .ENB (1'b1),
  .CLKB (CLK), .WEB (WEB), .RSTB (1'b0));
endmodule

However, passing the INIT_0x attributes in this manner does not initialize the memory contents for synthesis since all synthesis tools have their own mechanism for passing attributes to the implementation netlist. For references on today's synthesis tools, refer to the BlockRAM Instantiation and Initialization for Synthesis table.

Table 6-12  BlockRAM Instantiation and Initialization for Synthesis

Another method for passing the INIT_0x attributes to the Alliance tools is through the use of a UCF file. For example, the following statement defines the initialization string for the code example above.

INST U0 INIT_00 = 5555aaaa5555aaaa5555aaaa5555aaaa5555aaaa;
INST U0 INIT_01 = 5555aaaa5555aaaa5555aaaa5555aaaa5555aaaa;

The value of the INIT_0x string is a hexadecimal number that defines the initialization string.

CLKDLL

The duty cycle of the CLK0 output is 50-50 unless DUTY_CYCLE_CORRECTION attribute is set to FALSE, in which case the duty cycle is the same as that of the CLKIN.

The frequency of CLKDV is determined by the value assigned to the CLKDV_DIVIDE attribute. The default is 2.

The STARTUP_WAIT is not implemented in the model. Monitor the LOCK signal and use it to trigger the release of the GSR signal.

module clkdll_ex (CLKIN_P, RST_P, CLK0_P, CLK90_P, CLK180_P,
CLK270_P, CLK2X_P, CLKDV_P, LOCKED_P);
input CLKIN_P, RST_P;
output  CLK0_P, CLK90_P, CLK180_P, CLK270_P, CLK2X_P;
output  CLKDV_P;
// Active high indication that DLL is LOCKED to CLKIN
output  LOCKED_P;

wire CLKIN, CLK0;

// Input buffer on the clock
IBUFG U0 (.I (CLKIN_P), .O (CLKIN));

// GLOBAL CLOCK BUFFER on the delay compensated output
BUFG U2 (.I (CLK0), .O (CLK0_P));

// For RTL simulation only. The defparam will not synthesize.
// synopsys translate_off
// CLK0 divided by 1.5 2.0 2.5 3.0 4.0 5.0 8.0 or 16.0
defparam DLL0.CLKDV_DIVIDE = 4.0;
defparam DLL0.DUTY_CYCLE_CORRECTION = "FALSE";
// synopsys translate_on

// Instantiate the DLL primitive cell
CLKDLL DLL0 (.CLKIN (CLKIN), .CLKFB(CLK0_P), .RST (RST_P),
  .CLK0 (CLK0), .CLK90 (CLK90_P), .CLK180 (CLK180_P),
 .CLK270 (CLK270_P), .CLK2X (CLK2X_P), .CLKDV (CLKDV_P),
  .LOCKED (LOCKED_P));
endmodule

However, passing the CLKDLL attributes in this manner does not initialize the contents for synthesis. Please refer to your synthesis vendor's documentation since all synthesis tools have their own mechanism for passing attributes to the implementation netlist.

Another method for passing the CLKDLL attributes to the Alliance tools is through the use of an UCF file. For example, the following statement defines the initialization string for the code example above.

INST DLL0 CLKDV_DIVIDE = 4;
INST DLL0 DUTY_CYCLE_CORRECTION = FALSE;