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Synthesis and Simulation Design Guide
Chapter 6: Simulating Your Design

Running Simulation

When simulating, compile the Verilog source files in any order since Verilog is compile order independent. However, VHDL components must be compiled bottom-up due to order dependency. Xilinx recommends that you specify the test fixture file before the HDL netlist of your design, as in the following examples.

Xilinx recommends giving the name test to the main module in the test fixture file. This name is consistent with the name of the test fixture module that is written later in the design flow by NGD2VER during post-NGDBuild, post-MAP, or post-route simulation. If this naming consistency is maintained, you can use the same test fixture file for simulation at all stages of the design flow with minimal modification.

ModelSim Vcom

The following is information regarding ModelSim Vcom.

Using Shared Pre-Compiled Libraries

Simulation Libraries have to be compiled to compiled_lib_dir before using VCS/VCSi. See the "Compiling HDL Libraries" section for instruction on how to compile the Xilinx Verilog libraries.

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the command-line

vcom -work work_macro1.vhd logiblox_macro.vhd top_level.vhd testbench.vhd testbench_cfg.vhd

For timing simulation or post-Ngd2vhdl, the Simprims-based libraries are used. Specify the following at the command-line:

vcom -work work_design.vhd testbench.vhd

VSS

The following is information regarding VSS.

Using Shared Pre-Compiled Libraries

Simulation Libraries have to be compiled to compiled_lib_dir before using VSS vhdlan. See the "Compiling HDL Libraries" section for instruction on how to compile the Xilinx VHDL libraries.

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated components, or CORE Generator components), for RTL simulation, specify the following at the command-line.

vhdlan -i macro1.vhd 
vhdlan -i logiblox_macro.vhd
vhdlan -i top_level.vhd 
vhdlan -i testbench.vhd 
vhdlan -i testbench_cfg.vhd

For timing simulation or post-Ngd2vhdl, the Simprims-based libraries are used. Specify the following at the command-line.

vhdlan -i design.vhd 
vhdlan -i testbench.vhd
Note Make sure the WORK directory is created and that the .synopsys_vss.setup file exists and points to this directory.

For more information and a tutorial on running the VSS simulator, go to Synopsys tutorial at http://support.xilinx.com/support/techsup/tutorials.

Verilog-XL

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the command-line.

verilog -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v
testfixture.v design.v

The -y switch points the simulator to the HDL models.

For timing simulation or post-NGD2VER, the Simprims-based libraries are used. Specify the following at the command-line:

verilog -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v \ 
+libext+.v testfixture.v design.v

For more information on specifying Xilinx SimPrims library using the -ul switch with NGD2VER instead of using the -y switch in Verilog-XL, go to http://support.xilinx.com/techdocs/ 3167.htm.

Note You do not need to compile the libraries for Verilog-XL because it uses an interpretive compilation of the libraries.

NC-Verilog

There are two methods to run simulation with NC-Verilog.

  1. Using library source files with compile time options (similar to Verilog-XL).

  2. Using shared pre-compiled libraries.

Using Library Source Files With Compile Time Options

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the command-line:

ncxlmode +libext+.v -y $XILINX/verilog/src/unisims -y $XILINX/verilog/
src/simprims +incdir+$XILINX/verilog/src $XILINX/verilog/src/glbl.v
testfixture.v design.v

For timing simulation or post-NGD2VER, the Simprims-based libraries are used. Specify the following at the command-line.

ncxlmode -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v 
+libext+.v testfixture.v time_sim.v

Using Shared Pre-Compiled Libraries

Simulation Libraries have to be compiled to compiled_lib_dir before using NC-Verilog. See the "Compiling HDL Libraries" section for instruction on how to compile the Xilinx Verilog libraries.

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, edit the hdl.var and cds.lib files to specify the library mapping.

# cds.lib
DEFINE simprims_ver compiled_lib_dir/simprims_ver
DEFINE xilinxcorelib_ver compiled_lib_dir/xilinxcorelib_ver
DEFINE worklib worklib

# hdl.var
DEFINE VIEW_MAP ($VIEW_MAP, .v = v) DEFINE LIB_MAP ($LIB_MAP, 
compiled_lib_dir/unisims_ver = unisims_ver)
DEFINE LIB_MAP ($LIB_MAP, compiled_lib_dir/simprims_ver = 
simprims_ver)
DEFINE LIB_MAP ($LIB_MAP, compiled_lib_dir/simprims_ver = 
xilinxcorelib_ver)
DEFINE LIB_MAP ($LIB_MAP, + = worklib)
// After setting up the libraries, now compile and simulate the design:

ncvlog -messages -update $XILINX/verilog/src/glbl.v testfixture.v 
design.v
ncelab -messages testfixture_name glbl
ncsim -messages testfixture_name

The -update option of Ncvlog enables incremental compilation.

For timing simulation or post-Ngd2ver, the Simprims-based libraries are used. Specify the following at the command-line:

ncvlog -messages -update $XILINX/verilog/src/glbl.v 
testfixture.v time_sim.v
ncelab -messages -autosdf testfixture_name glbl
ncsim -messages testfixture_name

For more information on how to back-annotate the SDF file for timing simulation, go to http://support.xilinx.com/techdocs/947.htm.

VCS/VCSi

VCS and VCSi are identical except that VCS is more highly optimized, resulting in greater speed for RTL and mixed level designs. Pure gate level designs run with comparable speed. However, VCS and VCSi are guaranteed to provide the exact same simulation results. VCSi is invoked using the vcsi command rather than the vcs. command

There are two methods to run simulation with VCS/VCSi.

  1. Using library source files with compile time options (similar to Verilog-XL).

  2. Using shared pre-compiled libraries.

Using Library Source Files With Compile Time Options

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the command-line.

vcs -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims
incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v
-Mupdate -R testfixture.v design.v

For timing simulation or post-NGD2VER, the Simprims-based libraries are used. Specify the following at the command-line.

vcs +compsdf -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v+libext+.v -Mupdate -R testfixture.v
time_sim.v

The -R option automatically simulates the executable after compilation .

The -Mupdate option enables incremental compilation. Modules will be recompiled because of one of the following reasons:

  1. Target of a hierarchical reference has changed.

  2. Some compile time constant such as a parameter has changed.

  3. Ports of a module instantiated in the module has changed.

  4. Module inlining. For example, merging, internally in VCS, of a group of module definitions into a larger module definition which leads to faster simulation. These affected modules are again recompiled. This is done only once.

For more information on how to back-annotate the SDF file for timing simulation, go to http://support.xilinx.com/techdocs/6349.htm.

Using Shared Pre-Compiled Libraries

Simulation Libraries have to be compiled to compiled_lib_dir before using VCS/VCSi. See the "Compiling HDL Libraries" section for instruction on how to compile the Xilinx Verilog libraries.

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the command-line

vcs -Mupdate -Mlib=compiled_dir/unisims_ver -y $XILINX/verilog/src/
unisims -Mlib=compiled_dir/simprims_ver -y $XILINX/verilog/src/simprims 
-Mlib=compiled_dir/xilinxcorelib_ver +incdir+$XILINX/verilog/src
+libext+.v $XILINX/verilog/src/glbl.v -R testfixture.v design.v

For timing simulation or post-NGD2VER, the Simprims-based libraries are used. Specify the following at the command-line.

vcs +compsdf -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v+libext+.v-Mupdate -R testfixture.v
time_sim.v

The -R option automatically simulates the executable after compilation. Finally, the -Mlib=compiled_lib_dir option provides VCS with a central place to look for the descriptor information before it compiles a module and a central place to get the object files when it links together the executable.

The -Mupdate option enables incremental compilation. Modules will be recompiled because of one of the following reasons:

  1. Target of a hierarchical reference has changed.

  2. Some compile time constant such as a parameter has changed.

  3. Ports of a module instantiated in the module has changed.

  4. Module inlining. For example, merging, internally in VCS, of a group of module definitions into a larger module definition which leads to faster simulation. These affected modules are again recompiled. This is done only once.

For more information on how to back-annotate the SDF file for timing simulation, go to http://support.xilinx.com/techdocs/6349.htm.

ModelSim Vlog

There are two methods to run simulation with ModelSim Vlog.

  1. Using library source files with compile time options (similar to Verilog-XL).

  2. Using shared pre-compiled libraries.

Using Library Source Files With Compile Time Options

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the ModelSim prompt:

set XILINX $env(XILINX)
vlog -y $XILINX/verilog/src/unisims -y $XILINX/verilog/src/simprims
+incdir+$XILINX/verilog/src +libext+.v $XILINX/verilog/src/glbl.v -incr
testfixture.v design.v
vsim testfixture glbl

For timing simulation or post-NGD2VER, the Simprims-based libraries are used. Specify the following at the ModelSim prompt:

vlog -y $XILINX/verilog/src/simprims $XILINX/verilog/src/glbl.v 
+libext+.v testfixture.v time_sim.v -incr
vsim testfixture glbl +libext+.v testfixture.v

The -incr option enables incremental compilation.

Using Shared Pre-Compiled Libraries

Simulation Libraries have to be compiled to compiled_lib_dir before usingModelSim Vlog. See the "Compiling HDL Libraries" section for instruction on how to compile the Xilinx Verilog libraries.

Depending on the makeup of the design (LogiBLOX, Xilinx instantiated primitives, or CORE Generator components), for RTL simulation, specify the following at the ModelSim prompt:

set XILINX $env(XILINX)
vlog $XILINX/verilog/src/glbl.v testfixture.v time_sim.v -incr
vsim -L unisims_ver -L simprims_ver -L xilinxcorelib_ver testfixture glbl

For timing simulation or post-NGD2VER, the Simprims-based libraries are used. Specify the following at the ModelSim prompt:

vlog $XILINX/verilog/src/glbl.v testfixture.v time_sim.v -incr 
vsim -L simprims_ver testfixture glbl

The -incr option enables incremental compilation. The -L compiled_lib_dir option provides VSIM with a library to search for design units instantiated from Verilog.

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