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XST Flow
XST is a Xilinx tool that synthesizes HDL designs to create EDIF netlists. This manual describes XST support for Xilinx devices, HDL languages, and design constraints. The manual explains how to use various design optimization and coding techniques when creating designs for use with XST.
Before you synthesize your design, you can set a variety of options for XST.
Select your top-level design in the Source window.
To set the options, right click Synthesize in the Process window.
Select Properties to display the Process Properties dialog box.
Set the desired Synthesis, HDL, and Xilinx Specific Options.
For a complete description of these options, refer to the "Setting Constraints and Options" section in the "Design Constraints" chapter.
When a design is ready to synthesize, you can invoke XST within the Project Navigator. With the top-level source file selected, double-click Synthesize in the Process window.
- Note To run XST from the command line, refer to the "Command Line Mode" chapter for details.
When synthesis is complete, view the results by double-clicking View Synthesis Report. Following is a portion of a sample report.
Figure 1-1 View Synthesis Report
