Log File Analysis

The XST log file related to FPGA optimization contains the following sections:

• Design optimization

• Resource usage report

• Timing report

Design Optimization

During design optimization, XST reports the following:

• Potential removal of equivalent flip-flops.

  Two flip-flops (latches) are equivalent when they have the same data and control pins

• Register replication

  Register replication is performed either for timing performance improvement or for satisfying maximum fanout constraints. Register replication can be turned off using the register_duplication constraint.

Following is a portion of the log file.

Starting low level synthesis...
Optimizing unit down4cnt ...
Optimizing unit doc_readwrite ...
...
Optimizing unit doc ...
Building and optimizing final netlist ...
Register doc_readwrite_state_D2 equivalent to doc_readwrite_cnt_ld has been removed
Register I_cci_i2c_wr_l equivalent to wr_l has been removed
Register doc_reset_I_reset_out has been replicated 2 time(s)
Register wr_l has been replicated 2 time(s)

Resource Usage

In the Final Report, the Cell Usage section reports the count of all the primitives used in the design. These primitives are classified in 8 groups:

• BELS

  This group contains all the logical cells that are basic elements of the Virtex technology, for example, LUTs, MUXCY, MUXF5, MUXF6.

• Flip-flops and Latches

  This group contains all the flip-flops and latches that are primitives of the Virtex technology, for example, FDR, FDRE, LD.

• RAMS

  This group contains all the RAMs.

• SHIFTERS

  This group contains all the shift registers that use the Virtex primitives. Namely SRL16, SRL16_1, SRL16E, SRL16E_1.

• Tri-States

  This group contains all the tri-state primitives, namely the BUFT.

• Clock Buffers

  This group contains all the clock buffers, namely BUFG, BUFGP, BUFGDLL.

• IO Buffers

  This group contains all the standard I/O buffers, except the clock buffer, namely IBUF, OBUF, IOBUF, OBUFT, IBUF_GTL ...

• LOGICAL

  This group contains all the logical cells primitives that are not basic elements, namely AND2, OR2, ...

• OTHER

  This group contains all the cells that have not been classified in the previous groups.

The following section is an example of an XST report for cell usage:

==================================================
...
Cell Usage :
# IO Buffers : 24
# OBUF : 8
# IBUF : 16
# BELS : 70
# LUT4 : 33
# LUT3 : 3
# LUT2 : 34
===================================================

Timing Report

At the end of the synthesis, XST reports the timing information for the design. The report shows the information for all four possible domains of a netlist: "register to register", "input to register", "register to outpad" and "inpad to outpad".

The following is an example of a timing report section in the XST log:

TIMING REPORT 
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
 FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE

Timing Summary: 
----------
Speed Grade: -6 
Minimum period: 7.523ns (Maximum Frequency: 132.926MHz)
Minimum input arrival time before clock: 8.945ns
Maximum output required time before clock: 14.220ns
Maximum combinational path delay: 10.899ns


Timing Detail: 
All values displayed in nanoseconds (ns)
Path from Clock 'sysclk' rising to Clock 'sysclk' rising : 7.523ns 
(Slack: -7.523ns)

                               Gate     Net 
Cell:in-out          fanout  Delay   Delay    Logical Name
----------------------------------------     ------------
FDC:C-Q               15   1.372   2.970    I_state_2
 begin scope: 'block1'
LUT3:I1-O              1   0.738   1.265    LUT_54
 end scope: 'block1'
LUT3:I0-O              1   0.738   0.000    I_next_state_2
FDC:D                       0.440            I_state_2
----------------------------------------
Total                              7.523ns

Timing Summary

The Timing Summary section gives a summary of the timing paths for all 4 domains:

The path from any clock to any clock in the design:

Minimum period: 7.523ns (Maximum Frequency: 132.926MHz)

The maximum path from all primary inputs to the sequential elements:

Minimum input arrival time before clock: 8.945ns

The maximum path from the sequential elements to all primary outputs:

Maximum output required time before clock: 14.220ns

The maximum path from inputs to outputs:

Maximum combinational path delay: 10.899ns

If there is no path in the domain concerned "No path found" is then printed instead of the value.

Timing Detail

The Timing Detail section describes the most critical path in detail for each region:

The start point and end point of the path, the maximum delay of this path, and the slack. The start and end points can be: Clock (with the phase: rising/falling) or Port:

Path from Clock 'sysclk' rising to Clock 'sysclk' rising : 7.523ns (Slack: -7.523ns)

The detailed path shows the cell type, the input and output of this gate, the fanout at the output, the gate delay, the net delay estimated and the name of the instance. When entering a hierarchical block, begin scope is printed, and similarly end scope is also printed when exiting a block.

The preceding report corresponds to the following schematic: