Improving Results

XST produces optimized netlists for the CPLD fitter which fits them in specified devices and creates the download programmable files. The CPLD low-level optimization of XST consists of logic minimization, subfunction collapsing, logic factorization, and logic decomposition. The result of the optimization process is an EDIF netlist corresponding to Boolean equation which will be reassembled by the CPLD fitter to fit the best the macrocell capacities. A special XST optimization process, known as equation shaping, is applied when the following options are selected:

• Flatten Hierarchy yes

• Optimization Effort 2

• Optimization Criteria speed

• Macro Generator auto

In this case, XST optimizes and reduces the Boolean equations to sizes accepted by device macrocells and forces the CPLD fitter to respect these operations through Keep/Collapse constraints written in the .ncf file. The .ncf file also contains an indication on the number of PTerms that you must specify when calling the CPLD fitter:

# Minimum value for -pterms option is n.

The equation shaping processing includes also a critical path optimization algorithm, which tries to reduce the number of levels of critical paths.

The CPLD fitter multi-level optimization is still recommended because the special optimizations done by the fitter (D to T flip-flop conversion, De Morgan Boolean expression selection).

How to Obtain Better Frequency?

The frequency depends on the number of logic levels (logic depth). In order to reduce the number of levels, the following options are recommended:

• Optimization Effort 2: this value implies the calling of the collapsing algorithm, which tries to reduces the number of levels without increasing the complexity beyond certain limits;

• Optimization Criteria speed: the priority is the reduction of number of levels.

The following tries, in this order, may give successively better results for frequency:

Try 1: only optimization effort 2 and speed optimization are selected. The other options have default values:

• Optimization effort 2

• Optimization Criteria speed

Try 2: the user hierarchy is flattened. In this case the optimization process has a global view of the design and the depth reduction may be better:

• Optimization effort 2

• Optimization Criteria area

• Flatten Hierarchy yes

Try 3: the macros are merged with surrounded logic, the design flattening is increased:

• Optimization effort 2

• Optimization Criteria area

• Flatten Hierarchy yes

• Macro Preserve no

Try 4: applying the equation shaping algorithm. The value of the -pterms option which must be used for the CPLD fitter is written as a warning message in the .ncf file. Options to be selected:

• Optimization effort 2

• Optimization Criteria speed

• Flatten Hierarchy yes

• Macro Generator Auto

The CPU time is increasing from try 1 to try 4.

Obtaining the best frequency depends also on the CPLD fitter optimization. Xilinx recommends running the multi-level optimization of the CPLD fitter with different values for the -pterms options, starting with 20 and finishing with 50 (except for equation shaping), with a step of 5. Statistically the value 30 gives the best results for frequency.

How to Fit a Large Design?

If a design does not fit in the selected device, over passing the number of device macrocells or device PTerm capacity, an area optimization must be selected for XST. Statistically, the best area results are obtained for the following options:

• Optimization effort 2

• Optimization Criteria area

• Default values for other options

Other options that may be tried for better fitting:

• Macro Generator LogiBlox. Some LogiBlox macros, especially adders/subtractors/addsubs, give better results in the number of macrocells and the results are improved when these macros are not merged with the surrounded logic;

• Optimization effort 1: for this effort, the collapsing algorithm is not called; sometimes the collapsing optimization increases the design complexity (number of PTerms) and the fitting may fail.