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Xilinx Synthesis Technology (XST) User Guide
Chapter 6: VHDL Language Support

Sequential Circuits

Sequential circuits can be described using sequential processes. The following two types of descriptions are allowed by XST:

Sequential Process with a Sensitivity List

A process is sequential when it is not a combinatorial process. In other words, a process is sequential when some assigned signals are not explicitly assigned in all paths of the statements. In this case, the hardware generated has an internal state or memory (flip-flops or latches).

Example 6-14 provides a template for describing sequential circuits. Also refer to the chapter describing macro inference for additional details (registers, counters, etc.).

Example 6-14: Sequential Process with Asynchronous, Synchronous Parts

process ( CLK, RST ) ...
begin
  if RST = '0' | ` 1'  then
    -- an asynchronous part may appear here
    -- optional part
    .......
  elsif CLK'EVENT | not CLK' STABLE
    and CLK = '0' | ` 1'  then
    -- synchronous part
    -- sequential statements may appear here
  end if;
end process;
Note Asynchronous signals must be declared in the sensitivity list. Otherwise, XST generates a warning and adds them to the sensitivity list. In this case, the behavior of the synthesis result may be different from the initial specification.

Sequential Process without a Sensitivity List

Sequential processes without a sensitivity list must contain a "wait" statement. The "wait" statement must be the first statement of the process and must be the only "wait" statement in the process. The condition in the "wait" statement must be a condition on the clock signal. Several "wait" statements in the same process are not accepted. An asynchronous part can not be specified within processes without a sensitivity list.

Example 6-15 shows the skeleton of such a process. The clock condition may be a falling or a rising edge.

Example 6-15: Sequential Process Without a Sensitivity List

process ...
begin
  wait until CLK'EVENT | not CLK' STABLE and CLK = ` 0' |'1';
    ... -- a synchronous part may be specified here.
end process;

Examples of Register and Counter Descriptions

Example 6-16 gives the description an 8-bit register using a process with a sensitivity list. In Example 6-17, the same example is described using a process without a sensitivity list containing a "wait" statement.

Example 6-16: 8 bit Register Description Using a Process with a Sensitivity List

entity EXAMPLE is
  port ( DI : in BIT_VECTOR (7 downto 0);
        CLK : in BIT;
        DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
begin
  process ( CLK )
  begin
    if CLK'EVENT and CLK = '1' then
      DO = DI ;
    end if;
  end process;
end ARCHI;

Example 6-17: 8 bit Register Description Using a Process without a Sensitivity List

entity EXAMPLE is
  port ( DI : in BIT_VECTOR (7 downto 0);
        CLK : in BIT;
        DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
begin
  process begin
    wait until CLK'EVENT and CLK = '1';
    DO = DI ;
  end process;
end ARCHI;

Example 6-18 gives the description of an 8-bit register with a clock signal and an asynchronous reset signal.

Example 6-18: 8 bit Register Description Using a Process with a Sensitivity List

entity EXAMPLE is
  port ( DI : in BIT_VECTOR (7 downto 0);
        CLK : in BIT;
        RST : in BIT;
        DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
begin
  process ( CLK, RST )
  begin
    if RST = '1' then
      DO = "00000000";
    elsif CLK'EVENT and CLK = '1' then 
      DO = DI ;
    end if;  
  end process; 
end ARCHI;

Example 6-19: 8 bit Counter Description Using a Process with a Sensitivity List

library ASYL;
use ASYL.PKG_ARITH.all;


entity EXAMPLE is
  port ( CLK : in BIT;
        RST : in BIT;
        DO : out BIT_VECTOR (7 downto 0) );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
begin
  process ( CLK, RST )
    variable COUNT : BIT_VECTOR (7 downto 0);
  begin
    if RST = '1' then
      COUNT := "00000000";
    elsif CLK'EVENT and CLK = '1' then
      COUNT := COUNT + "00000001";
    end if;
    DO = COUNT;
  end process;
end ARCHI;

Multiple Wait Statements Descriptions

Sequential circuits can be described with multiple wait statements in a process. When using XST, several rules must be respected to use multiple wait statements. These rules are as follows:

Example 6-20 uses multiple wait statements. This example describes a sequential circuit performing four different operations in sequence. The design cycle is delimited by two successive rising edges of the clock signal. A synchronous reset is defined providing a way to restart the sequence of operations at the beginning. The sequence of operations consists of assigning each of the four inputs: DATA1, DATA2, DATA3 and DATA4 to the output RESULT.

Example 6-20: Sequential Circuit Using Multiple Wait Statements

library IEEE;
use IEEE.STD_LOGIC_1164.all;


entity EXAMPLE is
  port ( DATA1, DATA2, DATA3, DATA4 : in STD_LOGIC_VECTOR (3 downto 0);
        RESULT : out STD_LOGIC_VECTOR (3 downto 0);
        CLK : in STD_LOGIC;
        RST : in STD_LOGIC := '0' );
end EXAMPLE;
architecture ARCH of EXAMPLE is
begin
  process begin
    SEQ_LOOP : loop
      wait until CLK'EVENT and CLK = '1';
      exit SEQ_LOOP when RST = '1';
      RESULT = DATA1; 


      wait until CLK'EVENT and CLK = '1';
      exit SEQ_LOOP when RST = '1';
      RESULT = DATA2;


      wait until CLK'EVENT and CLK = '1';
      exit SEQ_LOOP when RST = '1';
      RESULT = DATA3;


      wait until CLK'EVENT and CLK = '1';
      exit SEQ_LOOP when RST = '1';
      RESULT = DATA4;
    end loop;
  end process;
end ARCH;
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