Functions and Procedures

The declaration of a function or a procedure provides a mechanism for handling blocks used multiple times in a design. Functions and procedures can be declared in the declarative part of an entity, in an architecture, or in packages. The heading part contains the parameters: input parameters for functions and input, output and inout parameters for procedures. These parameters can be unconstrained; it means that they are not constrained to a given bound. The content is similar to the combinatorial process content.

Resolution functions are not supported except the one defined in the IEEE std_logic_1164 package.

Recursive function and procedure calls are also not supported.

Example 6-21 shows a function declared within a package. The "ADD" function declared here is a single bit adder. This function is called 4 times with the proper parameters in the architecture to create a 4-bit adder. The same example described using a procedure is shown in Example 6-22.

Example 6-21: Function Declaration and Function Call

package PKG is
  function ADD  (A,B, CIN : BIT )
  return BIT_VECTOR;
end PKG;


package body PKG is
  function ADD  (A,B, CIN : BIT )
  return BIT_VECTOR is
    variable S, COUT : BIT;
    variable RESULT : BIT_VECTOR (1 downto 0);
  begin
    S := A xor B xor CIN;
    COUT := (A and B) or (A and CIN) or (B and CIN);
    RESULT := COUT & S; 
    return RESULT;
  end ADD;
end PKG;


use work.PKG.all;


entity EXAMPLE is
  port ( A,B : in BIT_VECTOR (3 downto 0);
    CIN : in BIT;
    S : out BIT_VECTOR (3 downto 0);
    COUT: out BIT );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
  signal S0, S1, S2, S3 : BIT_VECTOR (1 downto 0);
  begin
    S0 = ADD ( A(0), B(0), CIN );
    S1 = ADD ( A(1), B(1), S0(1) );
    S2 = ADD ( A(2), B(2), S1(1) );
    S3 = ADD ( A(3), B(3), S2(1) );
    S = S3(0) & S2(0) & S1(0) & S0(0);
    COUT = S3(1);
end ARCHI; 

Example 6-22: Procedure Declaration and Procedure Call

package PKG is
  procedure ADD
    (A,B, CIN : in BIT;
      C : out BIT_VECTOR (1 downto 0) );
end PKG;
package body PKG is
  procedure ADD
    (A,B, CIN : in BIT;
      C : out BIT_VECTOR (1 downto 0) ) is
    variable S, COUT : BIT;
  begin
    S := A xor B xor CIN;
    COUT := (A and B) or (A and CIN) or (B and CIN);
    C := COUT & S;
  end ADD;
end PKG;

use work.PKG.all; 


entity EXAMPLE is
  port ( A,B : in BIT_VECTOR (3 downto 0);
    CIN : in BIT;
    S : out BIT_VECTOR (3 downto 0);
    COUT : out BIT );
end EXAMPLE;
architecture ARCHI of EXAMPLE is
begin
  process (A,B,CIN)
    variable S0, S1, S2, S3 : BIT_VECTOR (1 downto 0);
  begin
    ADD ( A(0), B(0), CIN, S0 );
    ADD ( A(1), B(1), S0(1), S1 );
    ADD ( A(2), B(2), S1(1), S2 );
    ADD ( A(3), B(3), S2(1), S3 ); 
    S = S3(0) & S2(0) & S1(0) & S0(0);
    COUT = S3(1);
  end process;
end ARCHI;