Verilog Meta Comments

XST supports meta comments in Verilog. Because Verilog does not offer a method for attribute definition such as VHDL, meta comments (comments that are understood by the Verilog parser) are used.

Meta comments can be used as follows:

• Set constraints on individual objects (for example, module, instance, net)

• Set directives on synthesis

  • parallel_case and full_case directives

  • translate_on translate_off directives

  • all tool specific directives (for example, syn_sharing), refer to the "Design Constraints" chapter for details.

Meta comments can be written using the C-style (/* ... */) or the Verilog style (// ...) for comments. C-style comments can be multiple line. Verilog style comments end at the end of the line.

XST supports the following:

• Both C-style and Verilog style meta comments

• translate_on translate_off directives

  // synthesis translate_on

  // synthesis translate_off

• parallel_case, full_case directives

  // synthesis parallel_case full_case

  // synthesis parallel_case

  // synthesis full_case

• Constraints on individual objects

  The general syntax is:

  // synthesis attribute AttributeName [of] ObjectName [is] AttributeValue

  Examples:

  // synthesis attribute RLOC of u123 is R11C1.S0

  // synthesis attribute HUSET u1 MY_SET

  // synthesis attribute fsm_extract of State2 is "yes"

  // synthesis attribute fsm_encoding of State2 is "gray"

For a full list of constraints, refer to the "Design Constraints" chapter.