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This manual describes Xilinx Synthesis Technology (XST) support for HDL languages, Xilinx devices, and constraints for the Foundation Series ISE software. The manual also discusses FPGA and CPLD optimization techniques and explains how to run XST from the Project Navigator Process window and command line.
This manual contains the following chapters and appendixes.
Chapter 1, "Introduction," provides a basic description of XST and lists supported architectures.
Chapter 2, "HDL Coding Techniques," describes a variety of VHDL and Verilog coding techniques that can be used for various digital logic circuits, such as registers, latches, tristates, RAMs, counters, accumulators, multiplexers, decoders, and arithmetic operations. The chapter also provides coding techniques for state machines and black boxes.
Chapter 3, "FPGA Optimization," explains how constraints can be used to optimize FPGAs and explains macro generation. The chapter also describes Virtex primitives that are supported.
Chapter 4, "CPLD Optimization," discusses CPLD synthesis options and the implementation details for macro generation.
Chapter 5, "Design Constraints," describes constraints supported for use with XST. The chapter explains which attributes and properties can be used with FPGAs, CPLDs, VHDL and Verilog. The chapter also explains how to set options from the Process Properties dialog box within Project Navigator.
Chapter 6, "VHDL Language Support," explains how VHDL is supported for XST. The chapter provides details on the VHDL language, supported constructs, and synthesis options in relationship to XST.
Chapter 7, "Verilog Language Support," describes XST support for Verilog constructs and meta comments.
Chapter 8, "Command Line Mode," describes how to run XST using the command line. The chapter describes the xst, run, and set commands and their options.
Appendix A, "XST Naming Conventions" discusses net naming and instance naming conventions.
For additional information, go to http://support.xilinx.com. The following table lists some of the resources you can access from this Web site. You can also directly access these resources using the provided URLs.
| Resource | Description/URL |
|---|---|
| Tutorials | Tutorials covering Xilinx design flows,
from design entry to verification and debugging http://support.xilinx.com/support/techsup/tutorials/index.htm |
| Answers
Database | Current listing of solution records for
the Xilinx software tools Search this database using the search function at http://support.xilinx.com/support/searchtd.htm |
| Application Notes | Descriptions of device-specific design
techniques and approaches http://support.xilinx.com/apps/appsweb.htm |
| Data Book | Pages from The Programmable Logic Data Book,
which contain device-specific information on Xilinx device characteristics,
including readback, boundary scan, configuration, length count,
and debugging http://support.xilinx.com/partinfo/databook.htm |
| Xcell Journals | Quarterly journals for Xilinx programmable
logic users http://support.xilinx.com/xcell/xcell.htm |
| Technical Tips | Latest news, design tips, and patch information
for the Xilinx design environment http://support.xilinx.com/support/techsup/journals/index.htm |
This manual uses the following conventions. An example illustrates each convention.
The following conventions are used for all documents.
Courier font indicates messages, prompts, and program files that the system displays.
speed grade: - 100
Courier bold indicates literal commands that you enter in a syntactical statement. However, braces "{ }" in Courier bold are not literal and square brackets "[ ]" in Courier bold are literal only in the case of bus specifications, such as bus [7:0].
rpt_del_net=
Courier bold also indicates commands that you select from a menu.
File
Open
Italic font denotes the following items.
Variables in a syntax statement for which you must supply values
edif2ngd design_name
References to other manuals
See the Development System Reference Guide for more information.
Emphasis in text
If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.
Square brackets "[ ]" indicate an optional entry or parameter. However, in bus specifications, such as bus [7:0], they are required.
edif2ngd [option_name] design_name
Braces "{ }" enclose a list of items from which you must choose one or more.
lowpwr ={on|off}
A vertical bar "|" separates items in a list of choices.
lowpwr ={on|off}
A vertical ellipsis indicates repetitive material that has been omitted.
IOB #1: Name = QOUT'
IOB #2: Name = CLKIN'
.
.
.
A horizontal ellipsis "...." indicates that an item can be repeated one or more times.
allow block block_name loc1 loc2locn;
The following conventions are used for online documents.
Red-underlined text indicates an interbook link, which is a cross-reference to another book. Click the red-underlined text to open the specified cross-reference.
Blue-underlined text indicates an intrabook link, which is a cross-reference within a book. Click the blue-underlined text to open the specified cross-reference.