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Creating FPGA Programming Files
After the design has been completely routed, you must configure the device so that it can execute the desired function. Xilinx's bitstream generation program, BitGen, takes a fully routed NCD (Native Circuit Description) file as its input and produces a configuration bitstream - a binary file with a .bit extension. The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA's memory cells, or it can be used to create a PROM file.
To create a configuration bitstream file for your design, use the following procedure.
Select the top-level source for the project in the Source window.
Click Create Programming File in the Process window.
Click Process
Run in the Project Navigator menu. (An alternative method is to double-click on Creating Programming File in the Process window.)The programming file creation process runs. If there are no errors, the top_source_name.bit file is created.
To view the Programming File Report in the ISE Report Viewer, double-click View Programming File Generation Report in the Process window.
The Programming File Report contains information about the BitGen run.
For a complete description of BitGen, see the "BitGen" chapter in the Development System Reference Guide.
Launching Programming Tools
When you are ready to configure the target device, you need to select a programming tool to use to configure the targeted device. The "Programming Tools" section contains a short overview of each tool.
To launch a programming tool, select the top-level source file in the Source window and then double-click on PROM File Formatter, Hardware Debugger, or JTAG Programmer in the Process window. The selected programming tool opens in its own window with the bitstream file loaded.
Setting Programming File Creation Options
The following sections describe the configuration options you can set prior to creating the programming file. Use the following procedure to access the Process Properties dialog box containing these options.
Click on a the top-level design source file in the Source window for a project that targets an FPGA device.
Right click on Create Programming File in the Process window.
Select Properties from the pull-down menu that appears.
The Process Properties dialog box for the Create Programming File process appears. An example is shown in the following figure.
Click on the tab corresponding to the type of options you want to set to display the available properties. You can set properties for the following program creation option groups: General Options, Configuration Options, Startup Options, and Readback Options.
- Note You can customize whether you want to display the Standard or Advanced list of properties in the Process Properties dialog boxes. Use the procedure described in the following section to display the Advanced properties.
Spartan2, Virtex, VirtexE, Virtex2 Options
This section includes descriptions of the available options for the Spartan2, Virtex, VirtexE, and Virtex2 designs. The options listed in each tab vary by architecture. The applicable architectures are identified when an option only applies to
certain architectures. In most cases, the Advanced and Standard displays (Edit Preferences Processes) are the same. Advanced display options are identified as appropriate.
General Options
The General Option for Program File processing are described in this section. An example of the General Options tab for a Virtex design is shown in the following figure.
Run Design Rules Checker (DRC)
Value: Enabled (default) / Disabled
The Run Design Rules Checker property enables or disables the design rule checker. Before generating the final bitstream, it is important to enable the DRC to evaluate the NCD file for problems that could prevent the design from functioning properly. By default, the Run Design Rules Checker option is enabled (checkbox is checked).
Create Bit File
Value: Enabled (default) / Disabled
The Create Bit File property enables and disables the creation of a design data or bitstream (.bit) file after you have verified the functionality and timing of your placed and routed design.
Create ASCII Configuration File
Value: Disabled (default) / Enabled
The Create ASCII Configuration File property enables and disables the creation of a rawbits text (RBT) file, which is an ASCII representation of your configuration bitstream.
Create Logic Allocation File
Value: Disabled (default) / Enabled
The Create Logic Allocation File property disables and enables the creation of a logic allocation file (top_source_name.ll). The Hardware Debugger uses the top_source_name.ll file to identify bits in the readback bitstream that represent the values of design I/Os, latches, and flip-flops.
Create Mask File
Value: Disabled (default) / Enabled
The Create Mask File property enables and disables the creation of a mask file (top_source_name.msk). The mask file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA.
Enable BitStream Compression
Value: Disabled (default) / Enabled
The Enable Bitstream Compression property allows you to enable or disable compression of the bitstream file.
Create Readback Data Files
Value: Disabled (default) / Enabled
The Create Readback Data Files property enables and disables the creation of a readback data file.
(Advanced Option) Global Clock Delays (Binary String)
Value: 1111 (default) / Binary String
The Global Clock Delay 0 (Gclkdel0), Global Clock Delay 1 (Gclkdel1), Global Clock Delay 2 (Gclkdel2), and Global Clock Delay 3 (Gclkdel3) properties allow you to add delays to the global clocks.
(Advanced Option) Enable Debugging of BitStream
Value: Disabled (default) / Enabled
The Enable Debugging of Bitstream property allows you to enable or disable debugging of the bitstream file.
Configuration Options
The Configuration Options for Program File processing are described in this section. An example of the Configuration Options tab for a Virtex design is shown in the following figure.
Configuration Rate
Value: 4 (default) / 5 / 7 / 8 / 9 / 10 / 13 / 15 / 20 / 26 / 30 / 34 / 41 / 45 / 51 / 55 / 60
Use the configuration rate option to select the rate in megahertz (MHz) for the internal configuration clock, GCLK, when configuring in master mode. The default is 4MHz.
Configuration Clk (Configuration Pins)
Value: Pull Up (default) / Float
The Configuration CLK property allows you to synchronize to an internal clock provided in the FPGA device. Pull Up (the default) enables the pull-up resistor on the Configuration CLK pin. The Float setting disables the pull-up resistor on the Configuration CLK pin.
Configuration Pins
Value: Pull Up (default) / Float / PullDown*
By default, the following configuration pins are set to PullUp to enable a pull-up on the pin. You can set a configuration pin to Float to disable both the pull-up and pull-down resistors on the pin or to PullDown, *except where noted otherwise, to enable a pull-down on the pin.
Configuration CLK
This pin can be set to PullUp or Float only.
Configuration Pin M0
Configuration Pin M1
Configuration Pin M2
Configuration Pin Program
This pin can be set to PullUp or Float only.
Configuration Pin Done
Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor on this pin.
Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.
Select Active PullUp to drive the DONE pin High with a CMOS driver.
JTAG Pins
Value: Pull Up (default) / Float / PullDown
By default, the following JTAG pins are set to PullUp to enable a pull-up on the pin. You can set a JTAG pin to Float to disable both the pull-up and pull-down resistors on the pin or to PullDown to enable a pull-down on the pin.
JTAG Pin TCK
JTAG Pin TDI
JTAG Pin TDO
JTAG Pin TMS
Code (8 Digit hexadecimal)
Value: Blank (default) / 8-digit hexadecimal number
The Code (8 Digit Hexadecimal) property allows you to assign a code in the User Identification Register. Enter an eight-digit hexadecimal ID code in the field. The hexadecimal digits are placed in the User ID Register.
Startup Options
The Startup Option for Program File processing are described in this section. An example of the Startup Options tab for a Virtex design is shown in the following figure.
Start-up Clock
Value: CCLK (default) / User Clock / JTAG Clock
The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock as described below.
CCLK
Select CCLK to synchronize to an internal clock provided in the FPGA device.
User Clock
Select User Clock to synchronize to a user-defined signal connected to the CLK pin of the startup symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.
JTAG Clock
Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.
Enable Internal Done Pipe
Value: Disable (default) / Enable
You should enable this option when the startup clock is running at high speeds. If you enable the option, the FPGA waits for the CFG_DONE signal that is delayed by one clock cycle instead of waiting for the pin itself.
Output Events
Value: See Table 16-1
There are five major output events which occur during a device startup.
Done (CFG_DONE pin going High)
Enable Outputs (device outputs no longer tri-stated)
Release Set/Reset (Global Set/Reset signal de-asserted)
Release Write Enable (Global Write Enable signal de-asserted)
Release DLL (DLL allowed to synchronize)
Depending on the settings for Startup Clock, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.
Table 16-1 Virtex, VirtexE, Virtex2, Spartan2 Output Events Options Matrix
| CCLK | User Clock | JTAG Clock | |
|---|---|---|---|
| DONE | C1-C6 | C1, U2-U6 | C1, J2-J6 |
| Enable Outputs | C1-C6, Done, Keep | C1, U2-U6, Done, Keep | C1, J2-J6, Done, Keep |
| Release Set/Reset | C1-C6, Done, Keep | C1, U2-U6, Done, Keep | C1, J2-J6, Done, Keep |
| Release Write Enable | C1-C6, Done, Keep | C1, U2-U6, Done, Keep | C1, J2-J6, Done, Keep |
| Release DLL | C0-C6, No Wait | C0-C1, U2-U6, No Wait | C0-C1, J2-J6, No Wait |
The definitions of the possible output events settings are as follows.
C0 - before the Cclk rising edge after the length count is met
C1 - first-Cclk rising edge after the length count is met
C2 - second-Cclk rising edge after the length count is met
C3 - third-Cclk rising edge after the length count is met
C4 - fourth-Cclk rising edge after the length count is met
C5 - fifth-Cclk rising edge after the length count is met
C6 - sixth-Cclk rising edge after the length count is met
U2 - second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
U3 - third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
U4 - fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
U5 - fifth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
U6 - sixth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
J2 - second-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)
J3 - third-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)
J4 - fourth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)
J5 - fifth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)
J6 - sixth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)
Done - when the CFG_DONE signal goes High
Keep - holds the pin at whatever level (High or Low) the pin is when the CFG_DONE signal goes High
No Wait - not synchronized to the startup clock; DLL synchronizes as soon as possible
Drive Done Pin High
Value: Disabled (default) / Enabled
The Drive Done Pin High property allows to control when the Done Pin goes High.
Readback Options
The Readback Options for Program File processing are described in this section. An example of the Readback Options tab for a Virtex design is shown in the following figure.
Use this tab to set the following Readback options:
Security
Value: Enable Readback and Reconfiguration (default) / Disable Readback / Disable Readback and Reconfiguration
The Security property allows you to select the readback options. You can set following Readback options from the Security drop-down list box.
Enable Readback and Reconfiguration
This option specifies readback options. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. After this option is run, external logic must drive the Cclk input to read back each data bit. The readback data appears on the !RDATA pin.
Disable Readback
This option disables readback. Use this option for design security. By disabling readback, configuration data is secure from being read from the FPGA. By default, this option is off.
Disable Readback and Reconfiguration
This option disables both readback and reconfiguration. Use this option for design security. By disabling readback and reconfiguration, configuration and reconfiguration data is secure from being read from the FPGA. By default, this option is off.
Generate Readback Bitstreem
Value: Disabled (default) / Enabled
The Generate Readback Bit Stream property allows you to enable the generation of a bitstream. A bitstream file is a stream of data that contains location information for logic on a device, that is, the placement of Configurable Logic Blocks (CLBs), Input/Output Blocks (IOBs), TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream configures the logic of a device and programs the device so that the states of that device can be read back.
Spartan, SpartanXL, XC4000 Options
This section includes descriptions of the available options for the Spartan, SpartanXL, and XC4000 designs. The options listed in each tab vary by architecture. The applicable architectures are identified when an option only applies to certain
architectures. In most cases, the Advanced and Standard displays (Edit Preferences Processes) are the same. Advanced display options are identified as appropriate.
General Options
The General Options for Program File processing are described in this section. An example of the General Options tab for a Spartan design is shown in the following figure.
Run Design Rules Checker (DRC)
Value: Enabled (default) / Disabled
The Run Design Rules Checker property enables or disables the design rule checker. Before generating the final bitstream, it is important to enable the DRC to evaluate the NCD file for problems that could prevent the design from functioning properly. By default, the Run Design Rules Checker option is enabled (checkbox is checked).
Create Bit File
Value: Enabled (default) / Disabled
The Create Bit File property enables and disables the creation of a design data or bitstream (.bit) file after you have verified the functionality and timing of your placed and routed design.
Create ASCII Configuration File
Value: Disabled (default) / Enabled
The Create ASCII Configuration File property enables and disables the creation of a rawbits text (RBT) file, which is an ASCII representation of your configuration bitstream.
Create Logic Allocation File
Value: Disabled (default) / Enabled
The Create Logic Allocation File property disables and enables the creation of a logic allocation file (top_source_name.ll). The Hardware Debugger uses the top_source_name.ll file to identify bits in the readback bitstream that represent the values of design I/Os, latches, and flip-flops.
Create Mask File
Value: Disabled (default) / Enabled
The Create Mask File property enables and disables the creation of a mask file (top_source_name.msk). The mask file is used to compare relevant bit locations for executing a readback of configuration data contained in an operating FPGA.
Tie Unused Interconnect
Value: Disabled (default) / Enabled
The Tie Unused Interconnect property allows you enable or disable whether all unused interconnects are tied to a logic Low or to a known level, keeping internal noise and power consumption to a minimum. When you enable this option, Design Rule Check (DRC) runs first. Then, the enabled Tie Unused Interconnect option does the following.
Ties all possible unused interconnect to unused CLB outputs and configures those outputs with a logic Low (F=0 or G=0)
Attempts to tie any remaining interconnect to CLB outputs which have not been designated as critical
Attempts to tie remaining interconnect to the global primary or secondary clock buffer outputs
Save Tied design (as _
filename
.ncd)
Value: Disabled (default) / Enabled
Use the Save Tied design property if you want the tied design saved as _filename.ncd.
Use Critical Nets Last
Value: Disabled (default) / Enabled
Enable the Use Critical Nets Last option to use the nets marked as critical to complete the tiedown process if necessary. You should only enable this option as a last resort after an attempt is made to use nets not marked critical.
You can only enable this option if you enabled the Tie all Interconnect option.
Tie All Interconnect
Value: Disabled (default) / Enabled
Enable the Tie All Interconnect option if you want to allow tie down to implement user signals. Enabling this option also forces tie down to fail if all nodes are not tied.
You can only enable this option if you also enable the Tie Unused Interconnect option.
Configuration Options
The Configuration Options for Program File processing are described in this section. An example of the Configuration Options tab for a Spartan design is shown in the following figure.
Enable Cyclic Redundancy Checking (CRC)
Value: Enabled (default) / Disabled
This option enables Cyclic Redundancy Checking (CRC) error checking during configuration. If enabled, the software calculates a running CRC and inserts a unique four-bit partial check at the end of each data frame in the configuration bitstream. This option allows the device to perform a CRC check on the bitstream during the configuration process. If disabled, the device performs a simple check for the 0110 pattern at the end of each frame in the configuration data. By default, this option is on.
Length Count Calculation
Value: Length (default) / DONE
The Length Count Calculation property controls when the device changes from configuration to user operation. The Length Count Alignment and DONE Alignment properties are discussed in The Programmable Logic Data Book.
Configuration Rate
Value: Slow (default) / Fast
Use the configuration rate option to select the rate for the internal configuration clock, GCLK, when configuring in master mode. You can set the rate to Slow (1MHz) or Fast (8MHz).
Configuration Pin Done
Value: Pull Up (default) / Float
Use the Configuration Pin Done option as follows:
Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor on this pin.
Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.
TDO Pin
Value: Float (default) / Pull Up / Pull Down
The TDO Pin option allows you to enable/disable the pull-up and /or pull down resistor on the TDO pin.The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available.
Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.
Select PullUp to enable a pull-up on the TDO pin.
Select PullDown to enable a pull-down on the TDO pin.
(XC4000 Only) Configuration Pin M0
Value: Float (default) / Pull Up / Pull Down
The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available.
Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.
Select PullUp to enable a pull-up on the M0 pin.
Select PullDown to enable a pull-down on the M0 pin.
(XC4000 Only) Configuration Pin M1
Value: Float (default) / Pull Up / Pull Down
The M1 pin can be used as tri-statable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available.
Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.
Select PullUp to enable a pull-up on the M1 pin.
Select PullDown to enable a pull-down on the M1 pin.
(XC4000 Only) Configuration Pin M2
Value: Float (default) / Pull Up / Pull Down
The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available.
Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.
Select PullUp to enable a pull-up on the M2 pin.
Select PullDown to enable a pull-down on the M2 pin.
(XC4000XLA only) Enable Express Mode Bitstream
Value: Disabled (default) / Enabled
This option enables express mode configuration. In this mode, configuration data is presented to the device in parallel format, and each new byte is clocked into the target device with every rising edge of the CCLK. This mode is eight times as fast as other configuration modes because data is processed at the rate of one byte per CCLK rather than one bit per CCLK.
(XC4000XLA only) Tolerate 5V I/O in 3.3V Circuitry
Value: On (default) / Off
This option allows a 3.3V device circuitry to tolerate 5V operation. For any device that operates on a mixed circuit environment with 3.3V and 5V, use this option. For any circuitry that operates exclusively on 3.3V, such as in a laptop computer, turn this option off. Turning off this option reduces power consumption.
- Note Disabling this option allows the device's clamping diodes to clamp ringing transients back to the 3.3V supply rail. A clamping diode is connected from each output to VCC. This option affects all I/O pins.
(XC4000XLA only) Enable BSCAN-Based Configuration
Value: Enabled (default) / Disabled
This option allows BSCAN-based configuration after the device is successfully configured. This feature allows board testing without the risk of reconfiguring XLA devices by toggling the TCK/TMS/TDI/TDO lines.
(XC4000XLA only) Allow Direct Sensing of DONE Configuration State (after BSCAN)
Value: Disabled (default) / Enabled
This option allows direct sensing of the DONE configuration state after performing a BSCAN-based configuration. This allows you to determine if a BSCAN-based configuration was successful.
Input Threshold Levels for IOBs
Value: TTL (default) / CMOS / Read from Design
Use the Input Threshold Levels for IOBs option to set one of the following input options:
Select TTL to specify TTL-compatible inputs.
Select CMOS to specify CMOS-compatible inputs.
Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.
Output Level for IOBs
Value: TTL (default) / CMOS / Read from Design
Use the Output Threshold Levels for IOBs option to set one of the following output options:
Select TTL to specify TTL-compatible inputs.
Select CMOS to specify CMOS-compatible inputs.
Select Read from Design to specify the TTL/CMOS input level included in the physical constraints (PCF) file.
(XC4000 Only) Address Lines
Value: 18 (default) / 22
Use this option to set the number of address lines that will be used by the FPGA during device configuration. Address lines are used to address data from a parallel PROM or flash memory device. Select either 18 or 22. If you choose 22, four extra device pins are activated as configuration address lines.
This option only applies to master parallel mode configuration. You must set this option in addition to setting the mode pins. Refer to The Programmable Logic Data Book for more information on address lines and master parallel mode configuration.
Startup Options
The Startup Options for Program File processing are described in this section. An example of the Startup Options tab for a Spartan design is shown in the following figure.
Start-Up Sequence
Value: Cclk_NoSync (default) / Cclk_Sync / Uclk_NoSync / Uclk_Sync
The Start-Up Sequence property allows you to specify the output events to occur according to the setting. By default, this field is set to Cclk_NoSynch. For more information regarding these settings, see The Programmable Logic Data Book.
Start-up Clock
Value: CCLK (default) / User Clock / JTAG Clock
The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock. The default is CCLK.
CCLK
Select CCLK to synchronize to an internal clock provided in the FPGA device.
User Clock
Select User Clock to synchronize to a user-defined signal connected to the CLK pin of the startup symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.
JTAG Clock
Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.
Synchronize I/O Startup Sequence to External Doneln Signal
Value: Disabled (default) / Enabled
The startup sequence can be synchronized with the signal on the DONE pin. Enable this option to begin the startup sequence when the signal on the DONE pin goes High. Typically, this option is enabled if the design configures a device connected in a daisy chain. Disable this option to begin the sequence when the configuration memory is full.
Output Events
Value: See Table 16-2
There are three major output events which occur during a device startup.
Done Active Event (DONE pin going High)
Enable Outputs (device outputs no longer tristated)
Release Set/Reset (Global Set/Reset signal deasserted)
Depending on the settings for Start-Up Clock and Synchronize I/O Startup Sequence to External DONE Input Pin, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.
Table 16-2 Spartan, SpartanXL, XC4000 Output Events Options Matrix
| CCLK
Sync | CCLK
No Sync | User Clock
Sync | User Clock
No Sync | |
|---|---|---|---|---|
| DONE | C1-C3 | C1-C4 | C1, U2 | C1, U2-U4 |
| Enable Outputs | C2, C3, DI, DI+1 | C2-C4 | U2, DI, DI+1, DI+2 | U2-U4 |
| Release Set/Reset | C2, C3,
DI, DI+1 | C2-C4 | U2, DI, DI+1, DI+2 | U2-U4 |
The definitions of the possible output events settings are as follows.
C1 - First-Cclk rising edge after the length count is met
C2 - Second-Cclk rising edge after the length count is met
C3 - Third-Cclk rising edge after the length count is met
C4 - Fourth-Cclk rising edge after the length count is met
U2 - Second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
U3 - Third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
U4 - Fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)
DI - When the DoneIn signal goes High
DI+1 - First-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High
DI+2 - Second-Cclk or valid-user-clock rising edge, depending on the selection of start-upClk, after DoneIn goes High
Readback Options
The Readback Options for Program File processing are described in this section. An example of the Readback Options tab for a Spartan design is shown in the following figure.
Enable Readback of Configuration Bitstream
Value: Disabled (default) / Enabled
Use this option to enable or disable the readback capability of the configuration bitstream. To enable the readback capability, you enable this option and include the READBACK symbol in your design. Enabling this option generates a .ll file.
Enable Aborting of Readback Sequence
Value: Disabled (default) / Enabled
Enable this option to abort the readback sequence. You can use this option to terminate the readback sequence when the device detects a High-to-Low transition on the TRIG pin of the READBACK symbol.
Set Readback clock to
Value: Cclk (default) / Rdbk
During the readback process, the data is clocked out synchronously. The source of the readback clock can be either the CCLK or a user clock. Select the Cclk value to clock out the readback data through an internal clock provided in the FPGA device. Select the Rdbk value to out the readback data through a user-defined signal connected to the CLK pin of the READBACK symbol.
