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At the end of a successful CPLD implementation, a design database file (top_source_name.vm6) is created. From this, a JEDEC programming file can be generated. The JTAG Programmer uses this JED file to configure XC9500/XL/XV CPLD devices.
To create a JED programming file for your design, use the following procedure.
Select the top-level source for the project in the Source window.
Click Create Programming File in the Process window.
Click Process
Run in the Project Navigator menu. (An alternative method is to double-click on Creating Programming File in the Process window.)
The programming file creation process runs. If there are no errors, the top_source_name.jed file is created.
When you are ready to configure the target device, you need to use the JTAG Programmer to configure the targeted device. The "Programming Tools" section contains a short overview of the JTAG Programmer.
To launch the JTAG Programmer, select the top-level source file in the Source window and then double-click on JTAG Programmer in the Process window. The TAG Programmer opens in its own window with the JED file loaded.
This section describes the programming options you can set prior to creating the programming file. Use the following procedure to access the Process Properties dialog box containing these options.
Click on a the top-level design source file in the Source window for a project that targets an FPGA device.
Right click on Create Programming File in the Process window.
Select Properties from the pulldown menu that appears.
The Process Properties dialog box (shown in the following figure) for the Create Programming File process appears.

You can set the following options for CPLD programming file creation:
Signature/User Code
Value: Blank (default) / Four-character text string
Enter a unique text string in the Value field to identify the configuration data. You can enter a string of up to four alphanumeric characters. The device programmer can read the signature, and the person running the device programmer can verify that the correct configuration data file is loaded. Use the JTAG Programmer to identify the configuration data signature (usercode) of a programmed XC9500 or XC9500XL device. The default is to use the top_source_name.
Jedec Test Vector File
Value: Disabled (default) / Enabled
Enable this option to include a TMV file in your JEDEC file. The TMV file is a test vector file generated when ABEL compiles a design containing user test vectors.