Programming Tools

After the programming file has been successfully created, you can use one of the programming tools described in this section to configure your device.

JTAG Programmer

The JTAG Programmer downloads, reads back, and verifies FPGA and CPLD design configuration data. It can also perform functional tests on any device and probe the internal logic states of your design.

The JTAG Programmer software can be used to configure both FPGAs and CPLDs and supports both the XChecker and the Parallel Cable III. This is a GUI based program. See the JTAG Programmer Guide for details. Also, see the Hardware User Guide for information about cable compatibility.

PROM File Formatter

A FPGA or daisy chain of FPGAs can be configured from serial or parallel PROMs. The PROM File Formatter can create MCS, EXO, or TEK style files. The files are read by a PROM programmer that turns the image into a PROM.

A HEX file can also be used to configure an FPGA or a daisy chai of FPGAs through a microprocessor. The file is sotred as a data structure in the microprocessor boot-up code.

The PROM File Formatter is available for FPGA designs only. The PROM File Formatter provides a graphical user interface that allows you to do the following.

• Format BIT files into a PROM file compatible with Xilinx and third-party PROM programmers

• Concatenate multiple bitstreams into a single PROM file for daisy chain applications

• Store several applications in the same PROM file

Hardware Debugger

The Hardware Debugger is a graphical interface that allows you to download an FPGA design to a device, verify the downloaded configuration, and display the internal states of the programmed device.

The Hardware debugger can download a BIT file or a PROM file: MCS, EXO, or TEK file formats. A BIT file contains configuration information for an FPGA device. Form more information on using the Hardware Debugger, see the Hardware Debugger Guide.