The first step in analyzing the detailed path information for a system-synchronous OFFSET IN constraint is to understand how the timing information of the OFFSET IN constraint is calculated. The OFFSET IN delay defines the external clock and data relationship of the input signals to the FPGA. In the system-synchronous interface, this relationship consists of the time that data becomes valid prior to the clock edge used to capture that data. Given the external relationship, the OFFSET IN timing check uses the internal clock and data path delays to calculate the clock to data timing relationship at the internal register, and to ensure the setup and hold requirements of that register are met. The external timing relationship and the internal path that is analyzed are shown below.

This analysis of this constraint automatically includes any clock phase adjustments along the clock path, such as from a DCM, and any clock jitter and phase uncertainties of the system. The resulting equation for determining the OFFSET IN slack is:

	Slack = Requirement - (Data Path - Clock Path + uncertainty)

The source-synchronous timing relationship and equation are shown in the timing diagram below.

For more information on the OFFSET IN constraint, see the Constraints Guide.