ISEUsing Partitions - What to do First
A Partition defines a source instance that is marked
for reuse. Partitions can be HDL, Schematic or EDIF source instances
at any level of the hierarchy. When a lower-level source instance
is defined as a Partition, the top module is automatically defined
as a Partition as well. Partitions are enabled by creating a Partition
for a node in the design hierarchy. In Verilog, the Partition is set
on a module instance. In VHDL the Partition is set on an entity architecture.
- Before synthesis, decide which nodes in the design hierarchy
will be Partitions. The design hierarchy is visible in the Project
Navigator graphical environment in the Sources tab.
- Load all the design files into the project to see the complete
design hierarchy.
- If using a Tcl environment, the command search
get returns the design hierarchy for the project. The
design hierarchy reflects the files added to the project with the xfile add command.
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