FPGA Design Flow Overview
The ISE® design flow comprises the following steps:
design entry, design synthesis, design implementation, and Xilinx® device
programming. Design verification, which includes both functional verification
and timing verification, takes places at different points during the
design flow. This section describes what to do during each step. For
additional details on each design step, click on a link below the
You can verify
the functionality of your design at different points in the design
flow as follows:
- Before synthesis, run behavioral simulation (also known as
- After Translate, run functional simulation (also known as gate-level
simulation), using the SIMPRIM library.
- After device programming, run in-circuit verification.
Synthesize your design.
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