ISE
FPGA Design Flow Overview
The ISE® design flow comprises the following steps: design entry, design synthesis, design implementation, and Xilinx® device programming. Design verification, which includes both functional verification and timing verification, takes places at different points during the design flow. This section describes what to do during each step. For additional details on each design step, click on a link below the following figure.
ImageDesign Synthesis and VerificationChipScope Pro Debugging OverviewConfiguration Overview
Design Entry
Create an ISE project as follows:
  1.  Create a project. Image
  2.  Create files and add them to your project, including a user constraints (UCF) file. Image
  3.  Add any existing files to your project. Image
  4.  Assign constraints such as timing constraints, pin assignments, and area constraints. Image
Functional Verification
You can verify the functionality of your design at different points in the design flow as follows:
  •  Before synthesis, run behavioral simulation (also known as RTL simulation). Image
  •  After Translate, run functional simulation (also known as gate-level simulation), using the SIMPRIM library. Image
  •  After device programming, run in-circuit verification. Image
Design Synthesis
Synthesize your design. Image
Design Implementation
Implement your design as follows:
  1.  Implement your design, which includes the following steps: Image
    •  Translate
    •  Map
    •  Place and Route
  2.  Review reports generated by the Implement Design process, such as the Map Report or Place & Route Report, and change any of the following to improve your design:
    •  Process properties Image
    •  Constraints Image
    •  Source files Image
  3.  Synthesize and implement your design again until design requirements are met.
Timing Verification
You can verify the timing of your design at different points in the design flow as follows:
  •  Run static timing analysis at the following points in the design flow:
    •  After Map Image
    •  After Place & Route Image
  •  Run timing simulation at the following points in the design flow:
    •  After Map (for a partial timing analysis of CLB and IOB delays) Image
    •  After Place and Route (for full timing analysis of block and net delays) Image
Xilinx Device Programming
Program your Xilinx device as follows:
  1.  Create a programming file (BIT) to program your FPGA. Image
  2.  Generate a PROM or ACE file for debugging or to download to your device. Image Optionally, create a JTAG file. Image
  3.  Use iMPACT to program the device with a programming cable. Image
See Also

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