Working with ABEL
ABEL-HDL is a hardware description language that supports a variety of behavioral input forms, including high-level equations, state diagrams, and truth tables. The Xilinx® ABEL version of the ABEL-HDL compiler and supporting software functionally verifies ABEL-HDL designs through simulation. The compiler then implements the designs in CPLDs.
You can enter designs in ABEL-HDL and verify them without taking the architecture of the target device into consideration. However, architecture-independent design descriptions require more comprehensive descriptions than their architecture-specific counterparts.
To Create an ABEL-HDL Module
Create your ABEL-HDL module as described in Creating a Source File, selecting ABEL-HDL Module as your source type. After you click Finish, the HDL file is added to the project and opens in the Project Navigator Workspace where you can define the behavior of the module.
Note When you create an ABEL-HDL Module, you can either define the module using the Define Module screen in the New Source Wizard, or you can click Next to bypass this screen, click Finish, and then define the module in the Project Navigator Workspace.
To Define the Behavior of an ABEL-HDL Module
The ISE® Language Templates provide a convenient method for you to insert pre-built language and functional code samples into your HDL file. For details, see Working with Language Templates.
Additional Information
For help working with ABEL, see the following resources:
  •  ABEL Reference Guide contains a comprehensive description of the ABEL language, including syntax of all ABEL commands, use of hierarchical design, and ABEL language examples.
  •  Keyword Help provides information on the use and syntax of ABEL keywords. Highlight the keyword in the ISE Text Editor in the Project Navigator Workspace, and press F1.  Keywords are shown in blue.

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