The digital clock manager (DCM) component implements a clock delay locked loop (DLL), a digital frequency synthesizer (DFS), and a digital phase shifter (DPS). The Library component used for Virtex®-4 and Virtex-5 is DCM_ADV. The Library component used for Spartan®-3A and Spartan-3E is DCM_SP.
Supported Devices
Virtex-II, Virtex-II Pro, Virtex-II Pro X, Virtex-4, Virtex-5, Spartan-3, Spartan-3E, Spartan-3A devices
Use the different functions for the following:
  •  DLL reduces the amount of clock skew to internal or external synchronous elements clocked by the outputs of the DCM.
  •  DFS derives new clock signals from the input clock by selecting a multiply and divide value to create an output clock of a new frequency.
  •  DPS offsets the phase of the output clock relative to the input clock in small increments.  
This component can only be instantiated. You can instantiate the component as follows:
  •  For schematic designs, instantiate the DCM Xilinx® Unified Library symbol.
  •  For HDL designs, do either of the following:
    •  Use the instantiation templates provided in the Libraries Guides.
    •  Use the instantiation templates provided with the Project Navigator Language Templates, which are described in Working with Language Templates.
  •  You can use the Architecture Wizard to create a DCM instance with the needed functionality. For more information, see Working with Architecture Wizard IP.
Additional Information
For additional information, see the following resources:
See Also

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