Test Bench Waveform Editor Overview

ISE Simulator (ISim)

Starting in 11.1, Xilinx® will no longer support the Test Bench Waveform Editor. When a project with a test bench waveform (TBW) is upgraded to 11.1, the TBW will be automatically converted to an HDL test bench and added to the project. Xilinx recommends using HDL test benches for new projects. For more information about creating an HDL test bench, go to:

ISE Language Templates for starter examples
Application Note XAPP199, Writing Efficient Test Benches
Synthesis and Simulation Design Guide

The ISim provides a Test Bench Waveform Editor in which you can graphically define your test benches or test fixtures. In the Test Bench Waveform (TBW), you can specify stimulus, and test bench lengths to verify your design without any knowledge of HDL or language scripting . The TBW you define can be added to your ISE project. You can then use this TBW to drive your design simulation, in the same way you would use an HDL test bench.

At any time you can view the HDL equivalent of your waveform using the View Generated Test Bench as HDL process in ISE.

While viewing and defining your TBW in the Test Bench Waveform Editor, edits made to the HDL source code, such as renaming ports, and adding or deleting signals, are reflected back in the graphic test bench waveform. COREGen For more information, see Modifying Ports.