Fuse with Precompiled HDL
The following
examples show how to invoke fuse using precompiled HDL.
For
VHDL using a top level entity architecture pair:
fuse -top top_level_entity_name(top_level_architecture_name)
For VHDL using a top level configuration:
fuse -top top_level_configuration
For Verilog
or mixed language design using all of the top level modules:
fuse -top top_level_module_name_1... -top top_level_module_name_n
-lib logicalLib1 -lib logicalLib2...
Fuse with HDL Source
Example
of fuse invoked using source VHDL
This example produces
an executable called tb.exe from VHDL source
listed in the project file called x.prj. The
top level design unit is architecture tb_arch of entity tb_ent. The contents of the project
file are as follows:
VHDL work x1.vhd
VHDL work x2.vhd
VHDL work x3.vhd
VHDL work tb.vhd
fuse -prj x.prj -top tb_ent(tb_arch)
-o tb.exe
To start simulation, execute the following:
tb.exe
Example of fuse
invoked using source Verilog
This example produces
an executable called tb.exe from Verilog source
listed in the project file called myproj.prj.
The top level design unit is tb defined in file tb.v. The contents of myproj.prj are
as follows:
Verilog work x1.v
Verilog work x2.v
Verilog work x3.v
Verilog work tb.v
Use the following command to run fuse:
fuse -prj x.prj -top tb -o tb.exe
To start simulation, execute the following:
tb.exe
Note For Verilog, if the design instantiates
any modules that have been compiled into any libraries other than
the work library, those libraries must be passed
to fuse using the -lib command line option
so that fuse will find those design units and link them into the simulation
executable.
Example of fuse invoked using mixed
VHDL/Verilog design
This example produces an executable
called tb.exe from Verilog and VHDL source code
listed in the project file called myproj.prj.
There are two top level design units: a VHDL top level called tb and a Verilog top level unit called glbl defined in tb.vhd and glbl.v respectively. The contents of myproj.prj are
as follows:
<>Verilog work x1.v
<>VHDLwork x2.vhd
<>Verilog work x3.v
<>VHDLwork x4.vhd
<>Verilog work glbl.v
<>VHDL work tb.vhd
Use the following command to run
fuse:
fuse -prj x.prj -top tb -top glbl -o tb.exe
To start simulation, execute the following:
tb.exe
Note For Mixed language
designs, for the modules on language boundary and for the Verilog
modules that have been compiled into any libraries other than the
work library, those libraries must be passed to fuse using
the
-lib command line option in the desired
search order so that fuse will find those design units and link them
into the simulation executable. For more information, see
Mixed Language Simulation
Overview.
Fuse with Command File Option
The following
example shows how to invoke fuse using the -f option:
fuse -f my_design.cmd
The following is an example of a command file for Verilog:
-nodebug
-intstyle xflow
-incremental
-top top_level_module_name_1
-top top_level_module_name_n
-lib logicalLib1
-lib logicalLib2