| -f <cmd_file> | You can save fuse command options in a text file for future use. This option reads and executes the saved options, specified in cmd_file. |
| -h | Displays all command line options and their usage. |
| -intstyle ise | xflow | silent | Use one of the specified styles for printing messages. Specify ise to print messages for the ISE Console tab or xflow to print messages for XFLOW. Specify silent to suppress all messages. By default all messages are printed. |
| -incremental | Compiles only the files that have changed since last compile. |
| -work <work_lib> [ = <lib_path> ] | Specifies the work library, and optionally, the physical path
for the work library. The physical path provided through this option
overrides mappings provided by the xilinxsim.ini file. The default work library is the logical library work. Work_lib is the logical name
of the specified work library optionally followed by lib_path, the path to the physical library. For example: mywork=C:home/worklib. |
| -lib <search_lib> [ = <lib_path> ] | Specifies other libraries and optionally the physical path
name for those libraries. Multiple -lib can
be used, and are treated as resource libraries. The physical path
provided through -lib overrides mappings provided
by the xilinxsim.ini file. More than one -lib can be specified. Search_lib is the logical name of the specified library optionally followed
by the lib_path, the path to the physical library.
For example: -lib mylib=C:home/mylib For Verilog designs, fuse searches for libraries in the order
that the -lib options are coded. For example: fuse -lib unsim -lib abcsim -lib xyzsim -top mytop Fuse searches for design units in unisim first then abcsim,
then xyzsim. If a design unit was defined in abcsim as well
as in xyzsim, the one in abcsim would be used as that appears before
xyzsim. If the order was changed to: fuse -lib
unisim -lib lyzsim -lib abcsim -top mytop And both
xyzsim and abcsim defined the same design unit, fuse would pick the
design unit from xyzsim. |
| -v <value> | Specifies the verbosity level for printing messages. Allowed values are 0, 1, or 2. The default is 0. |
| -nodebug | Generates output that has no information for debugging your HDL code during simulation. Output with no debug information runs simulation faster. The default is to generate HDL debuggable units. |
| -rangecheck | This option is for VHDL only. Specifies that if fuse calls
vhpcomp, that vhpcomp should run with the rangecheck option turned
on. Note This option does not effect checking of index ranges. ISim always checks the ranges of indexes. By default -rangecheck it is turned off. |
| -typdelay | This option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use typical delays. |
| -mindelay | This option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use fastest possible delays. |
| -maxdelay | This option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use worst case delays. |
| -i <include_path> | This option is for Verilog only. Specifies that if fuse calls vlogcomp, it should use the specified path for Verilog ’include directives. Each -i can be used for only one include path. More than one -i can be specified. Place quotes around paths with spaces. |
| -d <macro_definition> [ = <value> ] | This option is for Verilog only. Define the macros used in
Verilog files, and any value they require. More than one -d can be specified. Note There should be no space between
the "=" and the value as this space would be
interpreted as part of the value. |
| -o <sim_exe> | Specifies the name of the simulation executable output file.
The name of the file is sim_exe. If you do not
use this option, the default executable name is: work_lib/mod_name/platform/x.exe where:
|
| -prj <prj_file>.prj | Specifies a project file to use for input. A project
file contains a list of all the files associated with a design. It
is the main source file used by ISE. Prj_file is the project file and must have a prj extension. |
| -top <top_design_unit> | Specifies the highest level file of a precompiled Verilog or
VHDL design. Top_design_unit can be specified
as:
|
| -j <value> | This is a beta feature which is not fully tested. Specifies the number of sub-compilation jobs to be run in parallel.
The default is 0. |