Simulation (UNISIMS, SIMPRIMS, NGDANNO, NGD2EDIF, NGD2VHDL, NVD2VER)

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The following issues pertain to Simulation:

1.   Title: 4.2i UNISIMS, SIMPRIMS - Limitations in the DLL and DCM functional and Timing simulation models (VHDL, Verilog).

Description: There are some known limitations in the functionality of the DLL and DCM models. Some issues are bugs which will be fixed, and others are features that are not easily implementable in simulation and are thus not scheduled for fixing at this point. The list of known issues is maintained at the following Answer Record:

Reference:       http://support.xilinx.com/techdocs/10861.htm

2.   Title: 4.2i UNISIMS - Instance name not reported for memory collision in RAMB16* Components (Verilog).

Description: When using the Verilog UNISIM RAMB16* Dual-Port RAM components, if a memory collision is detected, the error message does not report the instance name. Please take special care to avoid memory collisions during simulation and device operation.

Reference:       http://support.xilinx.com/techdocs/12012.htm

3.   Title: 4.2i UNISIMS - Incorrect collision detection for some stimulus combinations in RAMB4* Component (Verilog).

Description: Using the Verilog UNISIM RAMB4 Dual-Port RAM components, if the same clock is being used for clock port A and port B, proper collision detection is not correctly identified. Please ensure that you do not read from the same port that is being written to on the same clock cycle.

Reference:       http://support.xilinx.com/techdocs/12012.htm

4.   Title: 4.2i SIMPRIMS - RAMB16* models do not allow varying the severity of collisions (VHDL).

Description: VHDL SIMPRIM X_RAMB16* Dual-port Block RAM components do not allow the user to vary the severity of the memory collisions. Due to this, the simulation stops when it runs into a memory collision. Please take special care to avoid memory collisions during simulation and device operation.

Reference:       http://support.xilinx.com/techdocs/12012.htm

5. Title: 4.2i SIMPRIMS - RAMB16* Dual -port BRAM components do not allow you to vary the severity of the memory collisions.

Description: Simulation stops when it runs into a memory collision. Please take special care to avoid memory collisions during simulation and device operaion.

Reference: http://support.xilinx.com/techdocs/12012

6.   Title: 4.2i SIMPRIMS, NGD2VHDL - In Post-NGDBUILD VHDL simulation, an error appears if the keyword "OPEN" is applied to input ports.

Description: In VHDL, the keyword "OPEN" can be applied to outputs only. If this keyword is applied to INPUT ports, then this error happens.

Reference: http://support.xilinx.com/techdocs/12179.htm

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7. Title: 4.2i SIMPRIMS - The collision warning message is one clock cycle late if there is a collision and CLKA and CLKB are the same signal (Verilog).

Description: Using the Verilog SIMPRIM RAMB4 Dual-Port RAM components, if the same clock is being used for clock port A and port B, the collision warning message is one clock cycle late.

Reference: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=12012

8. Title: 4.2i SIMPRIMS - In certain high-speed designs, some signal transitions get "swallowed" by the primitives and thus do not propagate the correct signal (VHDL, Verilog).

Description: In certain cases with high-speed VHDL or Verilog gate-level, timing simulation signal transitions may get "swallowed" within certain primitive components and therefore not propagate the proper signal transitions in simulation. This is due to the inertial delay specifications used by the simulation models. Refer to the solutions listed below for the workaround.

Reference: VHDL: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=11758

Verilog: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=9872

EDIF: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=12178

9. Title: 4.2i Simulation Models - Model Technology, Verilog NT wrappers for GT are incorrect.

Description: The GT SWIFT simulation wrapper files in the

$xilinx\verilog\smartmodel\nt\wrappers are incorrect. There are several pins missing which result in an error during Verilog simulation.

Reference: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=13547