MultiLINX Cable

MultiLINX Cable

Figure 2-10 shows the top and bottom view of the MultiLINX Cable.

Figure 2-10 MultiLINX Cable

You can use the MultiLINX Cable to download and verify all Xilinx CPLDs and FPGAs. The MultiLINX Cable hardware communicates with the host over the Universal Serial Bus (USB) at up to 12M bits/sec, or at variable baud rates over an RS-232 interface at up to 57600 bits/sec.

You can access the following application notes with descriptions of device-specific design techniques and approaches from the support page at (http://support.xilinx.com/support/searchtd.htm).

"Getting Started with the MultiLINX Cable" application note is a quick reference to everything you need to know to use the MultiLINX Cable, including using a USB device, Mixed Voltage environments, and connections for all the supported Modes.

"Integrating MultiLINX Cable with Target System Design" application note describes how to set up a Prototype application for use with the MultiLINX Cable.

"Xilinx Cable Overview and Roadmap" application note describes all the cables, their capabilities, and associated software tools.

MultiLINX Power Requirements

The MultiLINX Cable gets its power from the User's circuit board. The cable power does not come from the USB port (nor the RS-232 port). The red (PWR) and black (GND) wires from Flying Wire Set #1 are connected to the VCC (red wire) and Ground (black wire) lines of the circuit board that is powering the Xilinx device.

The minimum input voltage to the cable is 2.5 V (.8 A). The maximum input voltage is 5 V (.4 A).

MultiLINX Cable and Flying Leads

The MultiLINX Cable is shipped with four sets of flying lead wires. A USB Cable and RS-232 Cable (with adapter) are also supplied.

Figure 2-11 shows the MultiLINX Cable hardware and flying lead connection wires.

Figure 2-11 MultiLINX Cable and Flying Lead Connectors

The MultiLINX Flying wires are described in the following tables.

Table 2-7 MultiLINX Pin Descriptions (Flying Lead Set #1)

Signal Name

Function

PWR

Power - Supplies VCC to cable (Works at multiple voltages 5V, 3.3V, and 2.5V).

GND

Ground - Supplies ground reference to cable.

Table 2-8 MultiLINX Slave Serial Pin Descriptions
(Flying Lead Set #1)

Signal Name

Function

CCLK

Configuration Clock - is the configuration clock pin, and the default clock for readback operation.

DONE (D/P)

Done/Program - Indicates that configuration loading is complete, and that the start-up sequence is in progress.

DIN

Data In - Provides configuration data to target system during configuration and is tristated at all other times.

PROG

Program - A Low indicates the device is clearing its configuration memory.

Use the Active Low signal to initiate the configuration process.

INIT

Initialize -- Initialization sequencing pin during configuration (indicates start of configuration).

A logical zero on this pin during configuration indicates a data error.

RST

Reset --Pin used to reset internal FPGA logic. Connection to this pin is optional during configuration.

Table 2-9 MultiLINX Boundary-Scan Pin Descriptions
(Flying Lead Set #2)

Signal Name

Function

RD (TDO)

Read Data -- MultiLINX input.

iMPACT receives the readback data through the RD pin after readback is initiated.

Pin used to initiate a readback of target FPGA. TDO is for JTAG (Boundary-Scan).

TDI

TCK

TMS

These pins are used for JTAG (Boundary-Scan) device configuration.

The JTAG/boundary scan pins function for FPGA and CPLD, ISP PROM, JTAG and SystemACE MPM operations.

Table 2-10 MultiLINX Select Map Pin Descriptions
(Flying Lead Sets 3&4)

Signal Name

Function

D0-D7

Data Bus -- This pin is used for Virtex SelectMAP Mode.

An 8 bit data bus supporting the SelectMAP and Express configuration modes.

CS0 (CS)

Chip Select -- CS on the Virtex.

The CS0/CS pin represents a chip select to the target FPGA during configuration.

CS1

Chip Select -- The CS1 pin represents Chip Select to FPGAs during configuration.

CS2

Chip Select -- The CS2 pin represents Chip Select to the FPGA while using the Peripheral configuration mode.

WS

Write Select -- The WS pin represents Write Select control for the Asynchronous Peripheral configuration mode.

RS (RDWR)

Read Select -- The RS pin represents Read Select control for the Asynchronous Peripheral configuration mode.

Read/Write -- The RDWR pin is used as an active high READ and an active low WRITE control signal to the Virtex FPGA.

RDY/BUSY

Busy Pin -- Busy pin on the Virtex.

Signal Name	Function
PWR	Power - Supplies VCC to cable (Works at multiple voltages 5V, 3.3V, and 2.5V).
GND	Ground - Supplies ground reference to cable.

Signal Name	Function
CCLK	Configuration Clock - is the configuration clock pin, and the default clock for readback operation.
DONE (D/P)	Done/Program - Indicates that configuration loading is complete, and that the start-up sequence is in progress.
DIN	Data In - Provides configuration data to target system during configuration and is tristated at all other times.
PROG	Program - A Low indicates the device is clearing its configuration memory. Use the Active Low signal to initiate the configuration process.
INIT	Initialize -- Initialization sequencing pin during configuration (indicates start of configuration). A logical zero on this pin during configuration indicates a data error.
RST	Reset --Pin used to reset internal FPGA logic. Connection to this pin is optional during configuration.

Signal Name	Function
RD (TDO)	Read Data -- MultiLINX input. iMPACT receives the readback data through the RD pin after readback is initiated. Pin used to initiate a readback of target FPGA. TDO is for JTAG (Boundary-Scan).
TDI TCK TMS	These pins are used for JTAG (Boundary-Scan) device configuration. The JTAG/boundary scan pins function for FPGA and CPLD, ISP PROM, JTAG and SystemACE MPM operations.

Signal Name	Function
D0-D7	Data Bus -- This pin is used for Virtex SelectMAP Mode. An 8 bit data bus supporting the SelectMAP and Express configuration modes.
CS0 (CS)	Chip Select -- CS on the Virtex. The CS0/CS pin represents a chip select to the target FPGA during configuration.
CS1	Chip Select -- The CS1 pin represents Chip Select to FPGAs during configuration.
CS2	Chip Select -- The CS2 pin represents Chip Select to the FPGA while using the Peripheral configuration mode.
WS	Write Select -- The WS pin represents Write Select control for the Asynchronous Peripheral configuration mode.
RS (RDWR)	Read Select -- The RS pin represents Read Select control for the Asynchronous Peripheral configuration mode. Read/Write -- The RDWR pin is used as an active high READ and an active low WRITE control signal to the Virtex FPGA.
RDY/BUSY	Busy Pin -- Busy pin on the Virtex.