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Xilinx Common Configuring and Programming Setups
This section provides the Xilinx user a quick summary of some of the more common configuration and programming setups. There are many other methodologies for configuring Xilinx devices. The following setups are commonly used to allow for easy prototyping of robust production setups. A brief description of the setup advantages, required software and hardware, and hardware connections is provided for each setup.
CPLD JTAG Chain Setup
The CPLD JTAG Chain is the most common programming method for CPLDs, since it can be used for both prototyping and production environments.
Requires only the four JTAG pins to configure and test the chain
Combination of Xilinx CPLD devices (XC9500/XL/XV, XPLA3, CoolRunnerII).
For Prototyping: Xilinx Cable (Parallel III, IV or MultiLINX)
For Production: Microprocessor (Embedded Solution), Automatic Test Equipment (ATE), or Third Party Programmer
Xilinx CPLD programming jedec files (ISE Foundation/Alliance or WebPACK software packages create the jedec file)
For Prototyping: iMPACT Software in Boundary-Scan mode
For Production: Xilinx CPLD programming jedec files are converted to Xilinx Serial Vector Files (.svf) for use with a microprocessor, ATE, or Third Party Programmer. See XAPP058 at: http://www.xilinx.com/xapp/xapp058.pdf
See the Xilinx ATE and Programmer webpages for more information
Hardware Considerations
The connections to implement a CPLD JTAG chain are shown in the Figure below.
Figure 3-5 CPLD JTAG Chain Connections
When using a JTAG Chain with mixed voltage devices, extra care must be taken to ensure the integrity between the devices. Refer to the device's data sheet for the appropriate voltage operating ranges. In this example, using a 5 V, 3.3 V, and 2.5 V device in a single JTAG chain, although not as typical, allows consideration for a mixed voltage chain to be discussed.
To accommodate both the 9500 (5 V) and 9500XV (2.5 V) devices, the VCCIO signals should be tied to 3.3 V. This drives the TDO pin on all of the devices at 3.3 V, which meets the voltage requirements. For the 9500XV, only the VCCIO bank (1 or 2) where the TDO pin is located needs to be driven at 3.3 V.
When using a cable with this setup, it should be driven at 3.3 V. This ensures that the TMS and TCK TAP pin values are within the required voltage ranges for all of the specified devices. Since the 5 V part receives slightly lower but acceptable signal levels, good signal integrity is another practice that should be given appropriate consideration. Refer to the following sections for tips and techniques to ensure proper integrity strength and general practices on implementing a CPLD JTAG chain.
General JTAG Checklist
Include buffers on TMS and TCK signals interleaved at various points for larger JTAG chains of more than five devices to account for unknown device impedance.
Make sure the VCC is within the rated value: 5 V ±5% for the XC9500 device, 3.3 V ±10% for XC9500XL/XPLA3 devices, and 2.5 V ±10% for the XC9500XV device.
Provide both 0.1 mF and 0.01 mF capacitors at every VCC point of the chip and attach them directly to the nearest ground.
XC9500/XL/XV Specific Checklist
The TDI and TMS (JTAG) pins have internal pullups for the XC9500/XL/XV families and do not require any external pullups since the pins are dedicated for JTAG use.
It is vital that the XC9500/XL/XV devices be provided with very clean (noise free) voltage supplied to the VCCINT pins within the correct range.
The JTAG Clock for the XC9500/XL devices, TCK, has a maximum frequency of 10 MHz.
When deciding the placement of devices in a mixed voltage chain, care should be taken to ensure compatibility. For instance, the XC9500XV parts are not 5 V tolerant, and care should be taken to ensure the device inputs are driven by the appropriate voltage levels.
XPLA3 Specific Checklist
The PortEn pin should be connected to ground when using dedicated JTAG pins as recommended in this programming setup example.
Note: If the JTAG pins need to be used as dual-purpose I/Os, the PortEn pin should be jumpered out. The PortEn pin is driven high to re-establish connection with the JTAG pins.
The XPLA3 JTAG pins should have an external 10 kW resistor placed on them to prevent them from floating.
The JTAG clock for the XPLA3 devices, TCK, has a maximum frequency of 10 MHz.
Software Implementation Considerations
The software jedec files need to be created to program the devices. In the implementation step, there are several options that can be modified. The only option whose default setting may need to be changed for 9500/XL/XV configuration purposes is "Create Programmable GND Pins on Unused I/O." By default this option is not selected. Check this option to prevent unused I/O from floating and drawing additional power.
For CoolRunner XPLA3 devices, two of the most important options for programming you should be aware of are described below:
"Pull Up Unused I/O Pins" - By default, this option is selected. This is the recommended state to prevent additional power draw due to the CMOS I/O.
"Reserve JTAG Port Pins for ISP" - By default, this option is selected. Deselect this option only if you intend the JTAG pins to be used as dual-purpose I/Os.
Software Download Considerations
The last step needed to complete the implementation of a CPLD JTAG Chain is programming the bitstream to the device. With the JTAG Chain programming, this can be done for both prototyping and production environments.
Prototyping Environment
In a prototyping environment, it is very common to use a Xilinx programmer, which comprises a stand-alone downloadable software module that requires a Xilinx cable and access to the JTAG pins of the devices.
Production Environment
In a production environment, ATEs or Third Party Programmers are more common. In general, these tools supply faster programming times, and in many cases, supply a means to program more devices at a given time.
For this environment, a jedec file is normally converted into a standard vector format (.svf) file. This file format is a standard widely accepted by vendors and is a common way to distribute programming files. This format is an optional output of the Xilinx programmers described above in the Prototyping section. A description of how these files are created in the Xilinx programmers can be found in the ATE guides. Chapter 2, "Creating SVF files" of the ATE document describes in detail how the files are generated.
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