Spartan/XL Master Serial and JTAG Combination Setup

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Serial mode and JTAG mode are two of the most commonly used configuration modes for the Spartan/XL devices.

• Advantages:
  • Versatile and cost-effective solution
  • Master Serial Mode provides a simple and robust configuration mode for production, and the JTAG Mode provides In-System programming support for flexibility when configuring a chain in the Prototyping stage.
• Hardware Used:
  • Any combination of Xilinx Spartan/XL and companion 17Sxx devices
  • For Prototyping:   Xilinx Cable (Parallel III or MultiLINX)
  • For Production:   Xilinx PROM and supporting Programmer /Software
• Software Used:
  • Xilinx FPGA programming bitstream (.bit files)
  • For Prototyping: iMPACT Software
  • For Production:     Xilinx iMPACT Software to create Xilinx PROM files (.mcs, .exo), and appropriate Third Party Programmer software

Hardware Considerations

The hardware connections used to implement the Master Serial/JTAG Mode combination are shown in figure 3-7. Hardware items you should be aware of are listed below:

1. When configuring with Boundary Scan/JTAG mode, you must hold the INIT pin low on power up to allow the device to enter the JTAG mode.

   Note Connect INIT to GND for JTAG mode.

2. Set the mode pins for Master-Serial mode for the Spartan/XL: M0=0 and M1=1
3. For the JTAG pins, place a pullup of 4.7 kW on the TMS pin to avoid inadvertent JTAG operations.
4. Allow access to the INIT and DONE pins for initial board debugging. These two pins provide valuable status information.
5. The maximum for the JTAG clock, TCK, for the Spartan/XL is 2-5 MHz.
6. The speed of the CCLK in Master mode varies depending on the mode:

Slow (0.5 MHz - 1.25 MHz) (bitgen option "Configuration Rate.")

Fast (4 MHz - 10 MHz) (bitgen option "Configuration Rate.")

Figure 3-7 Spartan/XL Master-Serial/JTAG Mode Connections

Software Design Entry Considerations

In the Spartan/XL family you must add a library element to keep the JTAG pins from being converted to regular I/O after configuration.

• For the Spartan/XL family, the JTAG pins are dual purpose. If JTAG operations are needed after initial device configuration for reconfiguring the device or for other JTAG functions, you must place the BSCAN symbol in the design. This allows the JTAG pins to be dedicated and not converted to regular I/O after configuration, which is the default behavior.
• For a schematic example, the library element is shown in Figure 3-8. The four JTAG pins (TMS, TCK, TDI, and TDO) are the only pins that must be connected to maintain the JTAG pins. The TDO1, TDO2, DRCK, SEL1, SEL2, and IDLE are special-purpose pins for custom logic and should be left unconnected.

Figure 3-8 Boundary-Scan Spartan/XL Schematic Symbol

Software Implementation Considerations

After you have established the hardware setup, create the software bitstreams to prepare for programming the devices. When using this configuration setup with the Spartan/XL devices, consider the following software implementation options when generating the bitstream:

• "Configuration Rate" - is an implementation option that controls the speed of the CCLK in Master Serial mode. The speeds are described in the "Hardware Considerations" section above.
• "Enable BSCAN-Based Configuration" - is an implementation option that, when disabled, inhibits the BSCAN-based configuration after the device is successfully configured. This feature allows board testing without the risk of reconfiguring the Spartan/XL device by toggling the TCK/TMS/TDI/TDO lines.

For more detailed information or information on command line options, refer to the Development Systems Reference Guide.

Software Download Considerations

After the bitstream has been created, the download stage follows:

Prototyping

In this setup for prototyping, use the Xilinx iMPACT Configuration tool with a Xilinx cable to download the bitstream from the PC to the device. To achieve this, you need access to the four JTAG pins of the Spartan/XL device.

• Use the Xilinx Programming software, iMPACT, to download the bitstream to the part. Always be certain to use the latest version of the software.

Production

In the production environment, ensure that systems are not affected by power glitches or power down situations. The FPGA devices are volatile and a power outage erases the device contents. In order to ensure that the programmed data is not lost when the system is shut off, use a mode like Master Serial. The configuration data is permanently stored in the PROM in this example. Therefore, if a power outage occurs, the data in the PROM simply reconfigures the FPGA when power is regained. Below are the steps needed to program a XC17S00 PROM.

• Use the PROM Formatter tab in the File Generation mode in iMPACT (GUI version) or PROMgen (command line version) to format the bitstream into a PROM file.
• Use a third party programmer to program the PROM. See the website at: http://www.xilinx.com/support/programr/ps.htm