|
|
|
|
|
Glossary of Terms
This glossary contains definitions and explanations for terms commonly used in the iMPACT program.
The Xilinx ACE Flash memory card is a CompactFlash solid-state storage device with an on-card intelligent controller that manages interface protocols, data storage and retrieval, ECC, defect handling and diagnostics, power management, and clock control.
A synonym for a configuration bitstream file.
A data stream, also called BIT file, that contains location information of logic on a device, that is, the placement of CLBs, IOBs, TBUFs, pins, and routing elements. The bitstream also includes empty placeholders that are filled with the logical states sent by the device during a readback. Only the memory elements, such as flip-flops, RAMs, and CLB outputs, are mapped to these placeholders, because their contents are likely to change from one state to another. When downloaded to a device, a bitstream programs the device.
A bitstream file has a .bit extension.
Boundary-Scan mode is the method used for board-level testing of electronic assemblies. The primary objectives are the testing of chip I/O signals and the interconnections between ICs. It is the method for observing and controlling all new chip I/O signals through a standard interface called a Test Access Port (TAP). The boundary-scan architecture includes four dedicated I/O pins for control and is described in IEEE spec 1149.1.
A PROM that is read one byte at a time. The other PROM type is a serial PROM, which is read one bit at a time.
The pin of the configuration cable that connects the configuration clock to the device.
This pin has the same functionality as the ~DONE pin on the XC4000 and Spartan FPGAs. The CFG_DONE pin is a MultiLINX Target Interface Pin.
When asserted, this pin indicates that the FPGA is ready to receive configuration data. When de-asserted, the pin indicates that either the FPGA is in the power-up mode, or a configuration error has occurred. This pin has the same functionality as the INIT pin on the Spartan and XC4000 FPGAs. The CFG_RDY pin is a MultiLINX Target Interface Pin.
This pin has the same functionality as the ~PROGRAM pin on the XC4000 and Spartan FPGAs. The CFG_RESET pin is a MultiLINX Target Interface Pin.
A record of the commands that you executed during an iMPACT session.
CS on the Virtex; and CS0 on the XC4000 FPGAs. The CS/CS0 pin represents a chip select to the target FPGA during configuration. The CS/CS0 pin is a MultiLINX Target Interface Pin.
Chip Select to the XC4000 FPGAs during configuration. The CS1 pin is a MultiLINX Target Interface Pin.
The CS2 pin is a MultiLINX Target Interface Pin.
In the context of iMPACT, a data stream used to configure a set of devices that are connected in series such that the Dout pin of a device in the daisy chain is connected to the DIN pin of the next device. You can generate a daisy chain data stream by concatenating two or more bitstreams (BIT files) together using the PROM Formatter tab in the File Generation mode of iMPACT.
In the context of the PROM Formatter, a data stream is a collection of one or more concatenated BIT files used to implement a single user application. To implement multiple applications, concatenate data streams -- one data stream per application -- to form a multiple data stream PROM file that enables you to reprogram a single FPGA or a daisy chain.
The process of reading back or probing the states of a configured device to ensure that the device is behaving normally while in circuit.
The Data In pin of the configuration cable connects to the DIN pin of your target device. In serial mode, the DIN pin loads the bitstream data to the target FPGA.
This pin connects to the DONE pin of your target FPGA. It indicates the completion of the configuration process. During configuration, this pin is Low. After configuration, this pin is High.
Configuring or programming a device by sending bitstream data to the device.
An 8-bit data bus supporting the Express and SelectMAP configuration modes. The D0-D7 pins are MultiLINX Target Interface Pins.
Provides configuration data to downstream devices in a daisy-chain. The pin becomes a user I/O after configuration.
A PROM file format supported by the Xilinx tools. Its maximum address is 16,777,216. This format supports PROM files of up to
(8 x 16,777,216) = 134,217,728 bits.FPGA configuration mode (XC5200 only) in which configuration data is loaded into the FPGA in parallel; one byte per clock cycle instead of one bit per clock cycle.
The area located on the right side of the PROM Formatter window. The area presents a hierarchical view of the drives, directories, and BIT files in your system. The area is used to locate and select the BIT files that the PROM file will contain.
Ground (0 volt) pin of the configuration cable. This pin connects to the Ground pin of a power supply.
An ASCII hexadecimal version of the PROM data. It has unlimited data capacity.
Initialization pin on your configuration cable. This pin is connected to the INIT pin of your target device indicating when a device is ready to receive configuration data after power up. During configuration, INIT=0 indicates a configuration error.
The direction in which data is stored on your PROM. In the Up direction, the data is stored in ascending order, starting at a low address. In the Down direction, the data is stored in descending order, starting at a high address.
An Intel PROM format supported by the Xilinx tools. Its maximum address is 1,048,576. This format supports PROM files of up to (8 x 1,048,576) = 8,388,608 bits.
The mask file, (.msk) file indicates which bits are configuration bits and which ones are not. This file is needed to do a verify operation on a Virtex family device using the MultiLINX Cable. This file is generated during the implementation process (BitGen) if readback is enabled in the "Configuration Template".
The background against which other windows are displayed in the iMPACT menu bar.
The area located at the top of the iMPACT window. It includes the File, Cable, Download, Debug, View, Window, and Help menus.
The Program pin of your configuration cable provides a reprogram pulse to devices when connected to the PROG pin of the device.
A PROM file is the file output by the PROM Formatter tab in the File Generation mode of iMPACT, which can be used to program one or more devices. iMPACT supports the following PROM file formats: MCS (Intel MCS-86), EXO (Motorola EXORMacs), TEKHEX (Tektronix hexadecimal).
The area located on the left side of the PROM Formatter window. The area shows the structure of your PROM file. It is a hierarchical view of the data streams and BIT files in the PROM file.
An ASCII report file listing all the data streams and BIT files used to construct the PROM file, as well as the load direction and PROM file splitting information. The PROM Formatter uses this file to determine the structure and properties you have specified for the PROM file.
A raw BIT format file, the ASCII version of the BIT file.
The process of reading the logic downloaded to an FPGA device.
- A readback with a filter that extracts the configuration bits to verify that a design was downloaded correctly.
The readback data pin of the MultiLINX Cable. This pin connects to the RDATA pin of the device. When connected, the pin reads data from the programmed target device.
The RDWR pin is used as an active high READ and an active low WRITE control signal to the Virtex FPGA. The RDWR pin is a MultiLINX Target Interface Pin.
The RDY/BUSY pin is a MultiLINX Target Interface Pin.
Read Select control for the Asynchronous Peripheral configuration mode on XC4000 FPGAs. The RS pin is a MultiLINX Target Interface Pin.
SelectMAP mode is a configuration mode supported by the
Spartan-II, Virtex, Virtex-II, and Virtex-II Pro device families.Slave Serial mode is a configuration mode supported by the Virtex and Spartan devices.
A PROM whose data is read serially, one bit at a time. The other PROM type is a byte wide PROM, which is read one byte at a time.
The field located at the bottom of the iMPACT window. It provides information about the commands that you are about to select or that are already being processed.
System ACE is a Xilinx developed configuration environment that allows for space-efficient, pre-engineered, high-density configuration solutions for systems with multiple FPGAs. There are two versions of System ACE: System ACE CF and System ACE MPM.
In iMPACT, the Boundary-Scan clock pin.
In iMPACT, the Boundary-Scan data pin.
A Tektronix PROM format supported by Xilinx. Its maximum address is 65,536. This format supports PROM files of up to (8 x 65,536) = 524,288 bits.
In iMPACT, the Boundary-Scan select pin.
A field located under the menu bar at the top of the main window. It contains a series of buttons that execute some of the most frequently used commands. These buttons constitute an alternative to the menu commands.
The external trigger pin of the MultiLINX Cable. This pin is connected to an external signal used as a trigger. A Low to High transition on this pin signals the cables to initiate a readback.
Power pin of the configuration cable. This pin connects to the power pin of a target board.
The process of reading back the configuration data and comparing it to the original downloaded design to ensure that all of the design was received by the device.
Write Select control for the Asynchronous Peripheral configuration mode on XC4000 FPGAs during configuration. The WS pin is a MultiLINX Target Interface Pin.
|
|
|