Using Global Clock Buffers

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For designs with global signals, use global clock buffers to take advantage of the low-skew, high-drive capabilities of the dedicated global buffer tree of the target device. Your synthesis tool automatically inserts a clock buffer whenever an input signal drives a clock signal or whenever an internal clock signal reaches a certain fanout. The Xilinx implementation software automatically selects the clock buffer that is appropriate for your specified design architecture.

Some synthesis tools also limit global buffer insertions to match the number of buffers available on the device. Refer to your synthesis tool documentation for detailed information.

You can instantiate the clock buffers if your design requires a special architecture-specific buffer or if you want to specify how the clock buffer resources should be allocated.

Table 5-1 summarizes global buffer (BUFG) resources in Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Spartan-II devices.

Table 5-1 Global Buffer Resources

Buffer Type	Virtex	Virtex-E	Virtex-II/II Pro	Spartan-II
BUFG	4	4	N/A	4
BUFGMUX	N/A	N/A	16	N/A

Virtex/E/II/II Pro, and Spartan-II devices include two tiers of global routing resources referred to as primary global and secondary local clock routing resources.

Note In Virtex-II/II Pro, BUFG is available for instantiation, but will be implemented with BUFGMUX.

• The primary global routing resources are dedicated global nets with dedicated input pins that are designed to distribute high-fanout clock signals with minimal skew. Each global clock net can drive all CLB, IOB, and Block SelectRAM+ clock pins. The primary global nets may only be driven by the global buffers (BUFG), one for each global net. There are four primary global nets in Virtex/E and Spartan-II. There are sixteen in Virtex-II/II Pro.
• The secondary local clock routing resources consist of backbone lines or longlines. These secondary resources are more flexible than the primary resources since they are not restricted to routing clock signal only. These backbone lines are accessed differently between Virtex/E/Spartan-II and Virtex-II/II Pro devices as follows:
  • In Virtex/E and Spartan-II devices, there are 12 longlines across the top of the chip and 12 across bottom. From these lines, up to 12 unique signals per column can be distributed via the 12 longlines in the column. To use this, you must specify the USELOWSKEWLINES constraint in the UCF file. For more information on the USELOWSKEWLINES constraint syntax, refer to the "Constraints Guide".
  • In Virtex-II, longlines resources are more abundant. There are many ways in which the secondary clocks or high fanout signals can be routed using a pattern of resources that result in low skew. The Xilinx Implementation tools will automatically use these resources based on various constraints in your design. Additionally, the USELOWSKEWLINES constraint can be applied to access this routing resource.

Inserting Clock Buffers

Many synthesis tools automatically insert a global buffer (BUFG) when an input port drives a register's clock pin or when an internal clock signal reaches a certain fanout. A BUFGP (an IBUFG-BUFG connection) is inserted for the external clock whereas a BUFG is inserted for an internal clock. Most synthesis tools will also allow you to control BUFG insertions manually if you have more clock pins than the available BUFGs resources.

FPGA Express will infer up to four clock buffers for pure clock nets. FPGA Express will not infer a BUFG on a clock line that only drives one flip-flop.You can also instantiate clock buffers or assign them via the Express Constraints Editor.

Note Synthesis tools currently insert simple clock buffers, BUFGs, for all Virtex/E/II/II Pro and Spartan-II designs. For Virtex-II/II Pro , some tools provide an attribute to use BUFGMUX as an enabled clock buffer. To use BUFGMUX as a real clock multiplexer in Virtex-II/II Pro, it must be instantiated.

LeonardoSpectrum will force clock signals to global buffers when the resources are available. The best way to control unnecessary BUFG insertions is to turn off global buffer insertion, then use the buffer_sig attribute to push BUFGs onto the desired signals. By doing this the user will not have to instantiate any BUFG components. As long as "chip" options is used to optimize the IBUFs, they will be auto-inserted for the input.

The following is a syntax example of the buffer_sig attribute.

set_attribute -port clk1 -name buffer_sig -value BUFG 
set_attribute -port clk2 -name buffer_sig -value BUFG 

Synplify will assign a BUFG to any input signal that directly drives a clock. The maximum number of global buffers is defined as 4. Auto-insertion of the BUFG for internal clocks occur with a fanout threshold of 16 loads. To turn off automatic clock buffers insertion, use the syn_noclockbuf attribute. This attribute can be applied to the entire module/architecture or a specific signal. To change the maximum number of global buffer insertion, you may set an attribute in the .sdc file as follows.

define_global_attribute xc_global buffers (8) 

XST will assign a BUFG to any input signal that directly drives a clock. The default number of global buffers for the Virtex, Virtex-E, Virtex-II, Virtex-II Pro, and Spartan-II device is 4. Starting with software release 4.1i the default number of global buffer insertions for the Virtex-II device is 8. The number of BUFGs used for a design can be modified by the XST option bufg by either inserting it in HDL, the XST constraints file or via a command line switch. To specify a clock port on a black box as a clock, the 'sig_isclock' attribute can be specified either through HDL or the XST constraints file.

Refer to your synthesis tool documentation for a detailed syntax information.

Instantiating Global Clock Buffers

You can instantiate global buffers in your code as described in this section.

Instantiating Buffers Driven from a Port

You can instantiate global buffers and connect them to high-fanout ports in your code rather than inferring them from a synthesis tool script. If you do instantiate global buffers, verify that the Pad parameter is not specified for the buffer.

In Virtex/E/II and Spartan-II designs, synthesis tools insert BUFGP for clock signals which access a dedicated clock pin. To have a regular input pin to a clock buffer connection, you must use an IBUF-BUFG connection. This is done by instantiating BUFG after disabling global buffer insertion.

Instantiating Buffers Driven from Internal Logic

Some synthesis tools require you to instantiate a global buffer in your code to use the dedicated routing resource if a high-fanout signal is sourced from internal flip-flops or logic (such as a clock divider or multiplexed clock), or if a clock is driven from a non-dedicated I/O pin. The following VHDL and Verilog examples instantiate a BUFG for an internal multiplexed clock circuit.

Note Synplify will infer a global buffer for a signal that has 16 or greater fanouts.

• VHDL Example

  ----------------------------------------------- 
  -- CLOCK_MUX_BUFG.VHD Version 1.1            -- 
  -- This is an example of an instantiation of -- 
  -- global buffer (BUFG) from an internally   -- 
  -- driven signal, a multiplexed clock.       -- 
  -- March 2001                                -- 
  ----------------------------------------------- 
  library IEEE; 
  use IEEE.std_logic_1164.all; 
  entity clock_mux is 
              port (DATA, SEL: in STD_LOGIC; 
              SLOW_CLOCK, FAST_CLOCK: in  STD_LOGIC; 
              DOUT: out STD_LOGIC); 
  end clock_mux; 
  architecture XILINX of clock_mux is 
   
  signal CLOCK: STD_LOGIC; 
  signal CLOCK_GBUF: STD_LOGIC; 
  component BUFG 
      port (I: in  STD_LOGIC;  
            O: out STD_LOGIC); 
  end component; 
  begin 
   
  Clock_MUX: process (SEL, FAST_CLOCK, SLOW_CLOCK) 
      begin 
         if (SEL = '1') then  
                  CLOCK <= FAST_CLOCK; 
          else 
                CLOCK <= SLOW_CLOCK; 
          end if; 
      end process; 
   
  GBUF_FOR_MUX_CLOCK: BUFG 
     port map (I => CLOCK, 
                 O => CLOCK_GBUF); 
   
  Data_Path: process (CLOCK_GBUF) 
         begin 
         if (CLOCK_GBUF'event and CLOCK_GBUF='1')then 
             DOUT <= DATA; 
         end if; 
   end process; 
  end XILINX; 
  

• Verilog Example

       ////////////////////////////////////////////// 
       // CLOCK_MUX_BUFG.V Version 1.1                                             // 
     // This is an example of an instantiation of// 
   // global buffer (BUFG) from an internally  // 
   // driven signal, a multiplied clock.                                                 // 
   // March 2001                                                 // 
  /////////////////////////////////////////////// 
   
  module clock_mux(DATA,SEL,SLOW_CLOCK,FAST_CLOCK,
                      DOUT); 
         input  DATA, SEL; 
     input  SLOW_CLOCK, FAST_CLOCK; 
     output DOUT; 
   
      reg   CLOCK; 
      wire   CLOCK_GBUF; 
      reg    DOUT; 
          always @ (SEL or FAST_CLOCK or SLOW_CLOCK) 
          begin 
          if (SEL == 1'b1) 
              CLOCK <= FAST_CLOCK; 
          else 
              CLOCK <= SLOW_CLOCK; 
            end 
   
          BUFG GBUF_FOR_MUX_CLOCK (.O(CLOCK_GBUF), 
                                .I(CLOCK)); 
   
      always @ (posedge CLOCK_GBUF) 
          DOUT = DATA; 
  endmodule