Using Advanced Clock Management

Virtex/E, and Spartan-II devices feature Clock Delay-Locked Loop (CLKDLL) for advanced clock management. The CLKDLL can eliminate skew between the clock input pad and internal clock-input pins throughout the device. CLKDLL also provides four quadrature phases of the source clock. With CLKDLL you can eliminate clock-distribution delay, double the clock, or divide the clock. The CLKDLL also operates as a clock mirror. By driving the output from a DLL off-chip and then back on again, the CLKDLL can be used to de-skew a board level clock among multiple Virtex, Virtex-E, and Spartan-II devices. For detailed information on using CLKDLLs, refer to the "Libraries Guide" and application notes, XAPP 132 and XAPP 174 at http://www.xilinx.com/apps/xapp.htm.

In Virtex-II devices, the Digital Clock Manager (DCM) is available for advanced clock management. The DCM contains four main features listed below. For more information on the functionality of these features, refer to the "Libraries Guide" and the "Virtex-II Handbook."

Delay Locked Loop (DLL) -- The DLL feature is very similar to CLKDLL.
Digital Phase Shifter (DPS) -- The DPS provides a clock shifted by a fixed or variable phase skew.

Digital Frequency Synthesizer (DFS) -- The DFS produces a wide range of possible clock frequency related to the input clock.

Table 5-2 CLKDLL and DCM Resources
	Virtex/Spartan-II	Virtex-E	Virtex-II/II Pro
CLKDLL	4	8	N/A
DCM	N/A	N/A	4 - 12

Using CLKDLL (Virtex/E, Spartan II)

There are four CLKDLLs in each Virtex/Spartan-II device and eight in each Virtex-E device. There are also four global clock input buffers (IBUFG) in the Virtex/E and Spartan-II devices to bring external clocks in to the CLKDLL. The VHDL/Verilog example below shows a possible connection and usage of CLKDLL in your design. Cascading three CLKDLLs in Virtex/Spartan-II device is not allowed due to excessive jitter.

Synthesis tools do not infer CLKDLLs. The following examples shows how to instantiate CLKDLLs in your VHDL and Verilog code.

VHDL Example.

library IEEE;

use IEEE.std_logic_1164.all;

entity CLOCK_TEST is

port(

ACLK : in std_logic;

-- off chip feedback, connected to OUTBCLK on the board.

BCLK : in std_logic;

--OUT CLOCK

OUTBCLK : out std_logic;

DIN : in std_logic_vector(1 downto 0);

RESET : in std_logic;

QOUT : out std_logic_vector (1 downto 0);

-- CLKDLL lock signal

BCLK_LOCK : out std_logic

);

end CLOCK_TEST;

architecture RTL of CLOCK_TEST is

component IBUFG

port (

I : in std_logic;

O : out std_logic);

end component;

component BUFG

port (

I : in std_logic;

O : out std_logic);

end component;

component CLKDLL

port (

CLKIN : in std_logic;

CLKFB : in std_logic;

RST : in std_logic;

CLK0 : out std_logic;

CLK90 : out std_logic;

CLK180 : out std_logic;

CLK270 : out std_logic;

CLKDV : out std_logic;

CLK2X : out std_logic;

LOCKED : out std_logic);

end component;

-- Glock signals

signal ACLK_ibufg : std_logic;

signal BCLK_ibufg : std_logic;

signal ACLK_2x : std_logic;

signal ACLK_2x_design : std_logic;

signal ACLK_lock : std_logic;

begin

ACLK_ibufg_inst : IBUFG

port map (

I => ACLK,

O => ACLK_ibufg

);

BCLK_ibufg_inst : IBUFG

port map (

I => BCLK,

O => BCLK_ibufg

);

ACLK_bufg : BUFG

port map (

I => ACLK_2x,

O => ACLK_2x_design

);

ACLK_dll : CLKDLL

port map (

CLKIN => ACLK_ibufg,

CLKFB => ACLK_2x_design,

RST => '0',

CLK2X => ACLK_2x,

CLK0 => OPEN,

CLK90 => OPEN,

CLK180 => OPEN,

CLK270 => OPEN,

CLKDV => OPEN,

LOCKED => ACLK_lock

);

BCLK_dll_out : CLKDLL

port map (

CLKIN => ACLK_ibufg,

CLKFB => BCLK_ibufg,

RST => '0',

CLK2X => OUTBCLK,

CLK0 => OPEN,

CLK90 => OPEN,

CLK180 => OPEN,

CLK270 => OPEN,

CLKDV => OPEN,

LOCKED => BCLK_lock

);

process (ACLK_2x_design, RESET)

begin

if RESET = '1' then

QOUT <= "00";

elsif ACLK_2x_design'event and ACLK_2x_design = '1' then

if ACLK_lock = '1' then

QOUT <= DIN;

end if;

end process;

END RTL;

Note To use this example in Synplify, include the following library.

library virtex; 
use virtex.components.all;

Verilog Example.

// Verilog Example 
// In this example ACLK's frequency is doubled, used inside and outside the chip. 
// BCLK and OUTBCLK are connected in the board outside the chip. 
module clock_test(ACLK, DIN, QOUT, BCLK, OUTBCLK, BCLK_LOCK, RESET); 
 input   ACLK, BCLK; 
 input RESET; 
 input [1:0] DIN; 
 output [1:0] QOUT; 
output OUTBCLK, BCLK_LOCK; 
reg [1:0] QOUT; 
IBUFG CLK_ibufg_A 
      (.I (ACLK), 
      .O(ACLK_ibufg) 
      ); 
BUFG ACLK_bufg 
      (.I (ACLK_2x), 
       .O (ACLK_2x_design) 
     ); 
IBUFG CLK_ibufg_B 
      (.I (BCLK),     // connected to OUTBCLK outside 
      .O(BCLK_ibufg) 
      ); 
CLKDLL ACLK_dll_2x   // 2x clock 
      (.CLKIN(ACLK_ibufg), 
      .CLKFB(ACLK_2x_design), 
      .RST(1'b0), 
      .CLK2X(ACLK_2x), 
      .CLK0(), 
      .CLK90(), 
        .CLK180(), 
      .CLK270(), 
      .CLKDV(), 
      .LOCKED(ACLK_lock) 
      ); 
CLKDLL BCLK_dll_OUT  // off-chip synchronization 
      (.CLKIN(ACLK_ibufg), 
.CLKFB(BCLK_ibufg), // BCLK and OUTBCLK is connected outside the chip. 
.RST(1'b0), 
.CLK2X(OUTBCLK),  //connected to BCLK outside 
.CLK0(), 
.CLK90(), 
.CLK180(), 
.CLK270(), 
.CLKDV(), 
.LOCKED(BCLK_LOCK) 
      ); 
always @(posedge ACLK_2x_design or posedge RESET) 
begin 
if (RESET) 
 QOUT[1:0] <= 2'b00; 
else if (ACLK_lock) 
 QOUT[1:0] <= DIN[1:0]; 
end 
endmodule 
  Note  To use this example in Synplify, add the following line:

'include "<path_to>/virtex.v"

Using the Additional CLKDLL in Virtex-E

There are eight CLKDLLs in each Virtex-E device, with four located at the top and four at the bottom. Refer to the "DLLs in Virtex-E Devices" figure below. The basic operations of the DLLs in the Virtex-E devices remains the same as in the Virtex and Spartan-II devices, but the connections may have changed for some configurations.

Figure 5-2 DLLs in Virtex-E Devices

Two DLLs located in the same half-edge (top-left, top-right, bottom-right, bottom-left) can be connected together, without using a BUFG between the CLKDLLs, to generate a 4x clock. Refer to the "DLL Generation of 4x Clock in Virtex-E Devices" figure below.

Figure 5-3 DLL Generation of 4x Clock in Virtex-E Devices

Below are examples of coding a CLKDLL in both VHDL and Verilog.

VHDL Example.

library IEEE; 
use IEEE.std_logic_1164.all; 
entity CLOCK_TEST is 
  port( 
ACLK : in  std_logic; 
DIN : in  std_logic_vector(1 downto 0); 
RESET : in  std_logic; 
QOUT : out std_logic_vector (1 downto 0); 
    -- CLKDLL lock signal 
BCLK_LOCK           : out std_logic 
    ); 
end CLOCK_TEST; 
architecture RTL of CLOCK_TEST is 
  component IBUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
  component BUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
  component CLKDLL 
    port ( 
      CLKIN  : in std_logic; 
      CLKFB  : in std_logic; 
      RST    : in std_logic; 
      CLK0   : out std_logic; 
      CLK90  : out std_logic; 
      CLK180 : out std_logic; 
      CLK270 : out std_logic; 
      CLKDV : out std_logic; 
      CLK2X  : out std_logic; 
      LOCKED : out std_logic); 
end component; 
  -- Clock signals 
  signal ACLK_ibufg             : std_logic; 
  signal ACLK_2x, BCLK_4x       : std_logic; 
  signal BCLK_4x_design         : std_logic; 
  signal BCLK_lockin            : std_logic; 
begin 
  ACLK_ibufginst : IBUFG 
    port map ( 
      I => ACLK, 
      O => ACLK_ibufg 
      ); 
  BCLK_bufg: BUFG 
    port map ( 
      I => BCLK_4x, O => BCLK_4x_design); 
  ACLK_dll : CLKDLL 
    port map ( 
      CLKIN      => ACLK_ibufg, 
      CLKFB      => ACLK_2x, 
      RST        => '0', 
      CLK2X      => ACLK_2x, 
      CLK0       => OPEN, 
      CLK90      => OPEN, 
      CLK180     => OPEN, 
      CLK270     => OPEN, 
      CLKDV      => OPEN, 
      LOCKED     => OPEN 
      ); 
   BCLK_dll : CLKDLL 
     port map ( 
       CLKIN     => ACLK_2x, 
       CLKFB     => BCLK_4x_design, 
       RST       => '0', 
       CLK2X     => BCLK_4x, 
        CLK0      => OPEN, 
       CLK90     => OPEN, 
       CLK180    => OPEN, 
       CLK270    => OPEN, 
       CLKDV     => OPEN, 
       LOCKED    => BCLK_lockin 
       ); 
process (BCLK_4x_design, RESET) 
begin 
 if RESET = '1' then 
  QOUT <= "00"; 
 elsif BCLK_4x_design'event and BCLK_4x_design = '1'  
then 
  if BCLK_lockin = '1' then 
   QOUT <= DIN; 
  end if; 
 end if; 
end process; 
 BCLK_lock <= BCLK_lockin; 
END RTL; 
  Note  Synplify users need to add the following two lines,
library virtex; 
use virtex.components.all;

Verilog Example.

module clock_test(ACLK, DIN, QOUT, BCLK_LOCK, RESET); 
 input   ACLK; 
 input RESET; 
 input [1:0] DIN; 
 output [1:0] QOUT; 
 output BCLK_LOCK; 
reg [1:0] QOUT; 
IBUFG CLK_ibufg_A 
      (.I (ACLK), 
      .O(ACLK_ibufg) 
      ); 
BUFG BCLK_bufg 
      (.I (BCLK_4x), 
       .O (BCLK_4x_design) 
      ); 
CLKDLL ACLK_dll_2x   // 2x clock 
      (.CLKIN(ACLK_ibufg), 
      .CLKFB(ACLK_2x), 
      .RST(1'b0), 
      .CLK2X(ACLK_2x), 
      .CLK0(), 
      .CLK90(), 
      .CLK180(), 
      .CLK270(), 
      .CLKDV(), 
      .LOCKED() 
      ); 
CLKDLL BCLK_dll_4x  // 4x clock 
      (.CLKIN(ACLK_2x), 
      .CLKFB(BCLK_4x_design), // BCLK_4x after bufg 
      .RST(1'b0), 
      .CLK2X(BCLK_4x), 
      .CLK0(), 
      .CLK90(), 
.CLK180(), 
      .CLK270(), 
      .CLKDV(), 
      .LOCKED(BCLK_LOCK) 
      ); 
always @(posedge BCLK_4x_design or posedge RESET) 
begin 
if (RESET) 
 QOUT[1:0] <= 2'b00; 
else if (BCLK_LOCK) 
 QOUT[1:0] <= DIN[1:0]; 
end 
endmodule 
  Note  Synplify users should add the appropriate library. Please see the "Instantiating FPGA Primitives" section in this chapter.

Using BUFGDLL

BUFGDLL macro is the simplest way to provide zero propagation delay for a high-fanout on-chip clock from the external input. This macro uses the IBUFG, CLKDLL and BUFG primitive to implement the most basic DLL application. Refer to the "BUFGDLL Schematic" figure below.

Figure 5-4 BUFGDLL Schematic

In FPGA Express, use the Constraints Editor to change the global buffer insertion to BUFGDLL.

In LeonardoSpectrum, set the following attribute in the command line or TCL script.

set_attribute -port <CLOCK_PORT> -name PAD -value BUFGDLL

LeonardoSpectrum support implementation of BUFGDLL with CLKDLLHF component. To use this implementation, set the following attribute.

set_attribute -port <CLOCK_PORT> -name PAD -value BUFGDLLHF

In Synplify, set the following attribute in SDC file.

define_attribute <port_name> xc_clockbuftype {BUFGDLL}

This attribute can be applied to the clock port in HDL code as well.

In XST, the BUFGDLL can be used by the 'clock_buffer' constraint entered in either HDL or the XST constraints file. For more information on using XST specific constraints see the "XST User Guide."

CLKDLL Attributes

To specify how the signal on CLKDIV pin is frequency divided with respect to the CLK0 pin, the CLKDV_DIVIDE property can be set. The values allowed for this property are 1.5, 2, 2.5, 3, 4, 5, 8, or 16. The default is 2.

In HDL code, CLKDV_DIVIDE property is set as an attribute to the CLKDLL instance.

The following are VHDL and Verilog coding examples of CLKDLL attributes.

VHDL Example.

library IEEE; 
use IEEE.std_logic_1164.all; 
entity CLOCK_TEST is 
  port( 
    ACLK                : in  std_logic; 
    DIN : in  std_logic_vector(1 downto 0); 
    RESET               : in  std_logic; 
    QOUT : out std_logic_vector (1 downto 0) 
    ); 
end CLOCK_TEST; 
architecture RTL of CLOCK_TEST is 
  component IBUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
  component BUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
  component CLKDLL 
    port ( 
      CLKIN  : in std_logic; 
      CLKFB  : in std_logic; 
      RST    : in std_logic; 
      CLK0   : out std_logic; 
      CLK90  : out std_logic; 
      CLK180 : out std_logic; 
      CLK270 : out std_logic; 
      CLKDV : out std_logic; 
      CLK2X  : out std_logic; 
      LOCKED : out std_logic); 
end component; 
  -- Clock signals 
signal ACLK_ibufg             : std_logic; 
signal div_2, div_2_design    : std_logic; 
signal ACLK0, ACLK0bufg       : std_logic; 
signal logic_0                : std_logic; 
 
attribute CLKDV_DIVIDE: string; 
attribute CLKDV_DIVIDE of ACLK_dll : label is "2"; 
 
logic_0 <= '0'; 
 
begin 
  ACLK_ibufginst : IBUFG 
    port map ( 
      I => ACLK, 
      O => ACLK_ibufg 
      ); 
  ACLK_bufg: BUFG 
    port map ( 
      I => ACLK0, O => ACLK0bufg); 
  DIV_bufg: BUFG 
    port map ( 
      I => div_2, O => div_2_design); 
  ACLK_dll : CLKDLL 
    port map ( 
      CLKIN      => ACLK_ibufg, 
      CLKFB      => ACLK0bufg, 
      RST        => logic_0, 
      CLK2X      => OPEN, 
      CLK0       => ACLK0, 
      CLK90      => OPEN, 
      CLK180     => OPEN, 
      CLK270     => OPEN, 
      CLKDV      => div_2, 
      LOCKED     => OPEN 
      ); 
process (div_2_design, RESET) 
begin 
if RESET = '1' then 
  QOUT <= "00"; 
 elsif div_2_design'event and div_2_design = '1' then 
   QOUT <= DIN; 
 end if; 
end process; 
END RTL;

Verilog Example.

module clock_test(ACLK, DIN, QOUT, RESET); 
 input   ACLK; 
 input RESET; 
 input [1:0] DIN; 
 output [1:0] QOUT; 
reg [1:0] QOUT; 
IBUFG CLK_ibufg_A 
      (.I (ACLK), 
      .O(ACLK_ibufg) 
      ); 
BUFG div_CLK_bufg 
      (.I (div_2), 
       .O (div_2_design) 
      ); 
BUFG clk0_bufg ( .I(clk0), .O(clk_bufg)); 
CLKDLL ACLK_div_2   // div by 2 
      (.CLKIN(ACLK_ibufg), 
      .CLKFB(clk_bufg), 
      .RST(1'b0), 
      .CLK2X(), 
      .CLK0(clk0), 
      .CLK90(), 
      .CLK180(), 
      .CLK270(), 
      .CLKDV(div_2), 
      .LOCKED() 
);

//exemplar attribute ACLK_div_2 CLKDV_DIVIDE 2 
//synopsys attribute CLKDV_DIVIDE "2" 
//synthesis attribute CLKDV_DIVIDE of ACLK_div_2 is "2" 
always @(posedge div_2_design or posedge RESET) 
begin 
if (RESET) 
 QOUT[1:0] <= 2'b00; 
else 
 QOUT[1:0] <= DIN[1:0]; 
end 
endmodule

Using DCM In Virtex-II/II Pro

Using DCM in your Virtex-II design will improve routability between clock pads and global buffers. Most synthesis tools currently do not automatically infer DCM. Hence, the DCM has to be instantiated in your VHDL and Verilog designs. Please refer to the Design Considerations Chapter of the "Virtex-II Handbook" or the "Virtex-II Pro Handbook", respectively for information on the various features in the DCM. This book can be found on the Xilinx website at
http://www.xilinx.com.

The following examples shows how to instantiate DCM and apply a DCM attribute in VHDL and Verilog.

Note For more information on passing attributes in the HDL code to different synthesis vendors, refer to the "General HDL Coding Styles" chapter .

VHDL Example 
-- Using a DCM for Virtex-II (VHDL) 
-- 
-- This code uses the phased clock output CLK0 of 
-- the DCM 
-- The Spread Spectrum option is enabled using the 
-- attribute DSS_MODE set to SPREAD_8 
-- 
-- The following code passes the attribute for 
-- the synthesis tools Synplify, FPGA Express 
-- LeonardoSpectrum and XST. 
library IEEE; 
use IEEE.std_logic_1164.all; 
entity clock_block is 
  port ( 
    CLK_PAD             : in  std_logic; 
    SPREAD_SPECTRUM_YES : in  std_logic; 
    RST_DLL             : in  std_logic; 
    CLK_out             : out std_logic; 
    LOCKED              : out std_logic 
    ); 
end clock_block; 
architecture STRUCT of clock_block is 
  signal CLK, CLK_int, CLK_dcm : std_logic; 
  attribute DSS_MODE : string; 
  attribute DSS_MODE of U2: label is "SPREAD_8"; 
  component IBUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
  component BUFG 
    port ( 
      I : in  std_logic; 
      O : out std_logic); 
  end component; 
  component DCM is 
                   port ( 
                    CLKFB    : in  std_logic; 
                    CLKIN    : in  std_logic; 
                                   DSSEN    : in  std_logic; 
                    PSCLK    : in  std_logic; 
                    PSEN     : in  std_logic; 
                    PSINCDEC : in  std_logic; 
                    RST      : in  std_logic; 
                                      CLK0     : out std_logic; 
                    CLK90    : out std_logic; 
                    CLK180   : out std_logic; 
                    CLK270   : out std_logic; 
                    CLK2X    : out std_logic; 
                    CLK2X180 : out std_logic; 
                    CLKDV    : out std_logic; 
                    CLKFX    : out std_logic; 
                    CLKFX180 : out std_logic; 
                    LOCKED   : out std_logic; 
                    PSDONE   : out std_logic; 
                    STATUS   : out std_logic_vector 
 (7 downto 0)); 
  end component; 
 
signal logic_0 : std_logic; 
 
begin 
 
logic_0 <= '0'; 
 
U1 : IBUFG port map ( I => CLK_PAD, O => CLK_int); 
  U2 : DCM port map ( 
    CLKFB    => CLK, 
    CLKIN    => CLK_int, 
    DSSEN    => SPREAD_SPECTRUM_YES, 
    PSCLK    => logic_0, 
    PSEN     => logic_0, 
    PSINCDEC => logic_0, 
    RST      => RST_DLL, 
    CLK0     => CLK_dcm, 
    LOCKED   => LOCKED); 
  U3 : BUFG port map (I => CLK_dcm, O => CLK); 
  CLK_out <= CLK; 
end architecture STRUCT;

Verilog Example

// Using a DCM for Virtex-II (Verilog) 
// 
// This code uses the phased clock output CLK0 of 
// the DCM 
// The Spread Spectrum option is enabled using the  
// attribute DSS_MODE set to SPREAD_8 
// 
// The following code passes the attribute for the  
// synthesis tools Synplify, FPGA Express, 
// LeonardoSpectrum and XST. 
module clock_top (clk_pad, spread_spectrum_yes, 
  rst_dll, 
    clk_out, locked); 
  input    clk_pad, spread_spectrum_yes, rst_dll; 
  output   clk_out, locked; 
  wire     clk, clk_int, clk_dcm; 
  IBUFG u1 (.I (clk_pad), .O (clk_int)); 
  DCM u2 (.CLKFB    (clk), 
       .CLKIN    (clk_int), 
       .DSSEN    (spread_spectrum_yes), 
       .PSCLK    (1'b0), 
       .PSEN     (1'b0), 
       .PSINCDEC (1'b0), 
       .RST      (rst_dll), 
       .CLK0     (clk_dcm), 
       .LOCKED   (locked)) /* synthesis  
  DSS_MODE="SPREAD_8" */;  
// synopsys attribute DSS_MODE "SPREAD_8" 
// exemplar attribute u2 DSS_MODE SPREAD_8  
// synthesis attribute DSS_MODE of u2 is "SPREAD_8"  
    BUFG u3(.I (clk_dcm), .O (clk)); 
    assign clk_out = clk; 
endmodule // clock_top 
  Note  Synplify users should add the appropriate library. Please see the "Instantiating FPGA Primitives" section in this chapter.

Attaching Multiple Attributes to CLKDLL and DCM

CLKDLLs and DCMs can be configured to various modes by attaching attributes during instantiation. In some cases, multiple attributes must be attached to get the desired configuration. The following HDL coding examples show how to attach multiple attribute to DCM components. The same method can be used to attach attributes to CLKDLL components.

See the "Libraries Guide" for available attributes for Virtex/Virtex-E CLKDLL. See the Virtex-II Handbook for the available attributes for Virtex-II DCM.

VHDL Example for Synplify

This example attaches multiple attributes to DCM components using the Synplify 'xc_prop' attribute.

Note Do not insert carriage returns between the values assigned to xc_props. A carriage return could cause Synplify to attach only part of the attributes.

-- VHDL code begin -- 
library IEEE;  
library virtex2; 
use IEEE.std_logic_1164.all;  
use virtex2.components.all; 
 
entity DCM_TOP is  
    port (  
           clock_in : in std_logic;  
           clock_out : out std_logic;  
           clock_with_ps_out : out std_logic;  
           reset : out std_logic  
           );  
end DCM_TOP;  
 
architecture XILINX of DCM_TOP is  
signal low, high : std_logic;  
signal dcm0_locked: std_logic; 
signal dcm1_locked: std_logic; 
signal clock : std_logic; 
signal clk0: std_logic; 
signal clk1: std_logic; 
signal clock_with_ps : std_logic; 
signal clock_out_int : std_logic; 
 
attribute xc_props : string;  
attribute xc_props of dcm0: label is "DLL_FREQUENCY_MODE = LOW,DUTY_CYCLE_CORRECTION = TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE = 1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = NONE,PHASE_SHIFT = 0";   
-- Do not insert any carriage return between the  
-- lines above. 
attribute xc_props of dcm1: label is "DLL_FREQUENCY_MODE =LOW,DUTY_CYCLE_CORRECTION = TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE = 1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = FIXED,PHASE_SHIFT = 0";  
-- Do not insert any carriage return between the 
-- the lines above. 
begin  
low <= '0'; 
high <= '1'; 
reset <= not(dcm0_locked and dcm1_locked); 
clock_with_ps_out <= clock_with_ps;                 
clock_out <= clock_out_int; 
 
U1 : IBUFG port map ( I => clock_in, O => clock);  
 
dcm0 : DCM port map (  
                         CLKFB => clock_out_int,  
                        CLKIN => clock,  
                        DSSEN => low,  
                        PSCLK => low,  
                        PSEN => low,  
                        PSINCDEC => low,  
                        RST => low, 
                        CLK0 => clk0, 
                        LOCKED => dcm0_locked); 
 
clk_buf0 : BUFG port map (I => clk0, O => clock_out_int);  
dcm1: DCM port map  ( 
    CLKFB => clock_with_ps, 
    CLKIN => clock, 
    DSSEN => low, 
    PSCLK   => low, 
    PSEN  => low, 
    PSINCDEC => low, 
    RST  => low, 
    CLK0 => clk1, 
    LOCKED => dcm1_locked 
);  
clk_buf1: BUFG port map( 
    I => clk1, 
    O => clock_with_ps 
); 
end XILINX;

Verilog Example for Synplify

This example attaches multiple attributes to DCM components using the Synplify 'xc_prop' attribute.

Note Do not insert carriage returns between the values assigned to xc_props. A carriage return could cause Synplify to attach only part of the attributes.

//Verilog code begin 
'include "/path_to/virtex2.v" 
module DCM_TOP( 
clock_in, 
clock_out, 
clock_with_ps_out, 
reset 
); 
 
input clock_in; 
output clock_out; 
output clock_with_ps_out; 
output reset; 
 
wire low; 
wire high; 
wire dcm0_locked; 
wire dcm1_locked; 
wire reset; 
wire clk0; 
wire clk1; 
 
assign low = 1'b0; 
assign high = 1'b1; 
assign reset = !(dcm0_locked & dcm1_locked); 
IBUFG CLOCK_IN ( 
.I(clock_in),  
.O(clock) 
); 
 
DCM DCM0 ( 
.CLKFB(clock_out),  
.CLKIN(clock),  
.DSSEN(low),  
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk0),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm0_locked),  
.PSDONE(),  
.STATUS() 
) 
/*synthesis xc_props="DLL_FREQUENCY_MODE = LOW,DUTY_CYCLE_CORRECTION = TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE = 1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = NONE,PHASE_SHIFT = 0" */; 
//Do not insert any carriage return between the  
//lines above. 
 
BUFG CLK_BUF0( 
.O(clock_out),  
.I(clk0) 
); 
 
DCM DCM1 ( 
.CLKFB(clock_with_ps_out),  
.CLKIN(clock),  
.DSSEN(low), 
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk1),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm1_locked),  
.PSDONE(),  
.STATUS() 
) /*synthesis xc_props="DLL_FREQUENCY_MODE =LOW,DUTY_CYCLE_CORRECTION = TRUE,STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE = 1,CLKFX_MULTIPLY = 1,CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = FIXED,PHASE_SHIFT = 0"  */; 
//Do not insert any carriage return between the  
//lines above. 
 
BUFG CLK_BUF1( 
.O(clock_with_ps_out),  
.I(clk1) 
); 
 
//synthesis translate_off 
defparam DCM0.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM0.STARTUP_WAIT = "TRUE"; 
defparam DCM0.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM0.CLKFX_DIVIDE = 1; 
defparam DCM0.CLKFX_MULTIPLY = 1; 
defparam DCM0.CLK_FEEDBACK = "1X"; 
defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE"; 
defparam DCM0.PHASE_SHIFT = "0"; 
 
defparam DCM1.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM1.STARTUP_WAIT = "TRUE"; 
defparam DCM1.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM1.CLKFX_DIVIDE = 1; 
defparam DCM1.CLKFX_MULTIPLY = 1; 
defparam DCM1.CLK_FEEDBACK = "1X"; 
defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED"; 
defparam DCM1.PHASE_SHIFT = "0"; 
//synthesis translate_on 
endmodule // DCM_TOP

VHDL Example for LeonardoSpectrum

library IEEE;  
use IEEE.std_logic_1164.all;  
 
entity DCM_TOP is  
    port (  
           clock_in : in std_logic;  
           clock_out : out std_logic;  
           clock_with_ps_out : out std_logic;  
           reset : out std_logic  
           );  
end DCM_TOP;  
 
architecture XILINX of DCM_TOP is  
signal low, high : std_logic;  
signal dcm0_locked: std_logic; 
signal dcm1_locked: std_logic; 
signal clock : std_logic; 
signal clk0: std_logic; 
signal clk1: std_logic; 
signal clock_with_ps : std_logic; 
signal clock_out_int : std_logic; 
 
attribute DLL_FREQUENCY_MODE : string; 
attribute DUTY_CYCLE_CORRECTION : string; 
attribute STARTUP_WAIT : string; 
attribute DFS_FREQUENCY_MODE : string; 
attribute CLKFX_DIVIDE : string; 
attribute CLKFX_MULTIPLY : string; 
attribute CLK_FEEDBACK : string; 
attribute CLKOUT_PHASE_SHIFT : string; 
attribute PHASE_SHIFT : string; 
  
attribute DLL_FREQUENCY_MODE of dcm0: label is "LOW"; 
attribute DUTY_CYCLE_CORRECTION of dcm0: label is "TRUE"; 
attribute STARTUP_WAIT of dcm0: label is "TRUE"; 
attribute DFS_FREQUENCY_MODE of dcm0: label is "LOW"; 
attribute CLKFX_DIVIDE of dcm0: label is "1"; 
attribute CLKFX_MULTIPLY of dcm0: label is "1"; 
attribute CLK_FEEDBACK of dcm0: label is  "1X"; 
attribute CLKOUT_PHASE_SHIFT of dcm0  : label is "NONE"; 
attribute PHASE_SHIFT of dcm0: label is  "0";   
 
attribute DLL_FREQUENCY_MODE of dcm1: label is "LOW"; 
attribute DUTY_CYCLE_CORRECTION of dcm1: label is "TRUE"; 
attribute STARTUP_WAIT of dcm1: label is "TRUE"; 
attribute DFS_FREQUENCY_MODE of dcm1: label is "LOW"; 
attribute CLKFX_DIVIDE of dcm1: label is "1"; 
attribute CLKFX_MULTIPLY of dcm1: label is "1"; 
attribute CLK_FEEDBACK of dcm1: label is  "1X"; 
attribute CLKOUT_PHASE_SHIFT of dcm1  : label is "FIXED"; 
attribute PHASE_SHIFT of dcm1: label is  "0"; 
 
component IBUFG is 
port ( 
 I : in std_logic; 
 O : out std_logic 
); 
end component; 
 
component BUFG is 
port ( 
 I : in std_logic; 
 O : out std_logic 
); 
end component; 
 
component DCM is  
port (  
      CLKFB : in std_logic;  
      CLKIN : in std_logic;  
      DSSEN : in std_logic;  
      PSCLK : in std_logic;  
      PSEN : in std_logic;  
      PSINCDEC : in std_logic;  
      RST : in std_logic;  
      CLK0 : out std_logic;  
      CLK90 : out std_logic;  
      CLK180 : out std_logic;  
      CLK270 : out std_logic;  
      CLK2X : out std_logic;  
      CLK2X180 : out std_logic;  
      CLKDV : out std_logic;  
      CLKFX : out std_logic;  
      CLKFX180 : out std_logic; 
      LOCKED : out std_logic;  
      PSDONE : out std_logic;  
      STATUS : out std_logic_vector (7 downto 0)); 
end component;  
 
begin  
low <= '0'; 
high <= '1'; 
reset <= not(dcm0_locked and dcm1_locked); 
clock_with_ps_out <= clock_with_ps;                 
clock_out <= clock_out_int; 
 
U1 : IBUFG port map ( I => clock_in, O => clock);  
 
dcm0 : DCM port map (  
                    CLKFB => clock_out_int,  
                    CLKIN => clock,  
                    DSSEN => low,  
                    PSCLK => low,  
                    PSEN => low,  
                    PSINCDEC => low,  
                    RST => low, 
                    CLK0 => clk0,  
                    LOCKED => dcm0_locked);  
 
clk_buf0 : BUFG port map (I => clk0, O => clock_out_int);  
 
dcm1: DCM port map  ( 
    CLKFB => clock_with_ps, 
    CLKIN => clock, 
    DSSEN => low, 
    PSCLK   => low, 
    PSEN  => low, 
    PSINCDEC => low, 
    RST  => low, 
    CLK0 => clk1, 
    LOCKED => dcm1_locked 
);  
 
clk_buf1: BUFG port map( 
    I => clk1, 
    O => clock_with_ps 
); 
 
end XILINX;

Verilog Example for LeonardoSpectrum

module DCM_TOP( 
clock_in, 
clock_out, 
clock_with_ps_out, 
reset 
); 
 
input clock_in; 
output clock_out; 
output clock_with_ps_out; 
output reset; 
 
wire low; 
wire high; 
wire dcm0_locked; 
wire dcm1_locked; 
wire reset; 
wire clk0; 
wire clk1; 
 
assign low = 1'b0; 
assign high = 1'b1; 
assign reset = !(dcm0_locked & dcm1_locked); 
 
IBUFG CLOCK_IN ( 
.I(clock_in),  
.O(clock) 
); 
 
DCM DCM0 ( 
.CLKFB(clock_out),  
.CLKIN(clock),  
.DSSEN(low),  
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk0),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm0_locked),  
.PSDONE(),  
.STATUS() 
); 
//exemplar attribute DCM0 DLL_FREQUENCY_MODE LOW 
//exemplar attribute DCM0 DUTY_CYCLE_CORRECTION 
TRUE 
//exemplar attribute DCM0 STARTUP_WAIT TRUE 
//exemplar attribute DCM0 DFS_FREQUENCY_MODE LOW 
//exemplar attribute DCM0 CLKFX_DIVIDE  1 
//exemplar attribute DCM0 CLKFX_MULTIPLY 1 
//exemplar attribute DCM0 CLK_FEEDBACK 1X 
//exemplar attribute DCM0 CLKOUT_PHASE_SHIFT NONE 
//exemplar attribute DCM0 PHASE_SHIFT  0 
 
BUFG CLK_BUF0( 
.O(clock_out), 
.I(clk0) 
); 
 
DCM DCM1 ( 
.CLKFB(clock_with_ps_out),  
.CLKIN(clock),  
.DSSEN(low), 
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk1),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm1_locked),  
.PSDONE(),  
.STATUS() 
); 
//exemplar attribute DCM1 DLL_FREQUENCY_MODE LOW 
//exemplar attribute DCM1 DUTY_CYCLE_CORRECTION 
TRUE 
//exemplar attribute DCM1 STARTUP_WAIT TRUE 
//exemplar attribute DCM1 DFS_FREQUENCY_MODE LOW 
//exemplar attribute DCM1 CLKFX_DIVIDE  1 
//exemplar attribute DCM1 CLKFX_MULTIPLY 1 
//exemplar attribute DCM1 CLK_FEEDBACK  1X 
//exemplar attribute DCM1 CLKOUT_PHASE_SHIFT FIXED 
//exemplar attribute DCM1 PHASE_SHIFT  0 
 
BUFG CLK_BUF1( 
.O(clock_with_ps_out),  
.I(clk1) 
); 
 
//exemplar translate_off 
defparam DCM0.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM0.STARTUP_WAIT = "TRUE"; 
defparam DCM0.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM0.CLKFX_DIVIDE = 1; 
defparam DCM0.CLKFX_MULTIPLY = 1; 
defparam DCM0.CLK_FEEDBACK = "1X"; 
defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE"; 
defparam DCM0.PHASE_SHIFT = "0"; 
 
defparam DCM1.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM1.STARTUP_WAIT = "TRUE"; 
defparam DCM1.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM1.CLKFX_DIVIDE = 1; 
defparam DCM1.CLKFX_MULTIPLY = 1; 
defparam DCM1.CLK_FEEDBACK = "1X"; 
defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED"; 
defparam DCM1.PHASE_SHIFT = "0"; 
//exemplar translate_on 
 
endmodule // DCM_TOP

Verilog Example for FPGA Express

module DCM_TOP( 
clock_in, 
clock_out, 
clock_with_ps_out, 
reset 
); 
 
input clock_in; 
output clock_out; 
output clock_with_ps_out; 
output reset; 
 
wire   low; 
wire  high; 
wire dcm0_locked; 
wire dcm1_locked; 
wire reset; 
wire clk0; 
wire clk1; 
 
assign low = 1'b0; 
assign high = 1'b1; 
assign reset = !(dcm0_locked & dcm1_locked); 
 
IBUFG CLOCK_IN ( 
.I(clock_in),  
.O(clock) 
); 
 
DCM DCM0 ( 
.CLKFB(clock_out),  
.CLKIN(clock),  
.DSSEN(low),  
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk0),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm0_locked),  
.PSDONE(),  
.STATUS() 
); 
/*synopsys attribute DLL_FREQUENCY_MODE "LOW" DUTY_CYCLE_CORRECTION "TRUE" STARTUP_WAIT "TRUE" DFS_FREQUENCY_MODE "LOW" CLKFX_DIVIDE  "1" CLKFX_MULTIPLY "1" CLK_FEEDBACK "1X" CLKOUT_PHASE_SHIFT "NONE" PHASE_SHIFT  "0" */ 
 
 
BUFG CLK_BUF0( 
.O(clock_out),  
.I(clk0) 
); 
 
DCM DCM1 ( 
.CLKFB(clock_with_ps_out),  
.CLKIN(clock),  
.DSSEN(low), 
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk1),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm1_locked),  
.PSDONE(),  
.STATUS() 
); 
/* synopsys attribute DLL_FREQUENCY_MODE "LOW" DUTY_CYCLE_CORRECTION "TRUE" STARTUP_WAIT "TRUE" DFS_FREQUENCY_MODE "LOW" CLKFX_DIVIDE "1" CLKFX_MULTIPLY "1" CLK_FEEDBACK "1X" CLKOUT_PHASE_SHIFT "FIXED" PHASE_SHIFT "0" */ 
 
BUFG CLK_BUF1( 
.O(clock_with_ps_out),  
.I(clk1) 
); 
 
//synopsys translate_off 
defparam DCM0.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM0.STARTUP_WAIT = "TRUE"; 
defparam DCM0.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM0.CLKFX_DIVIDE = 1; 
defparam DCM0.CLKFX_MULTIPLY = 1; 
defparam DCM0.CLK_FEEDBACK = "1X"; 
defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE"; 
defparam DCM0.PHASE_SHIFT = "0"; 
 
defparam DCM1.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM1.STARTUP_WAIT = "TRUE"; 
defparam DCM1.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM1.CLKFX_DIVIDE = 1; 
defparam DCM1.CLKFX_MULTIPLY = 1; 
defparam DCM1.CLK_FEEDBACK = "1X"; 
defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED"; 
defparam DCM1.PHASE_SHIFT = "0"; 
//synopsys translate_on 
 
endmodule // DCM_TOP

Verilog Example for XST

module DCM_TOP( 
clock_in, 
clock_out, 
clock_with_ps_out, 
reset 
); 
 
input clock_in; 
output clock_out; 
output clock_with_ps_out; 
output reset; 
 
wire   low; 
wire  high; 
wire dcm0_locked; 
wire dcm1_locked; 
wire reset; 
wire clk0; 
wire clk1; 
 
assign low = 1'b0; 
assign high = 1'b1; 
assign reset = !(dcm0_locked & dcm1_locked); 
 
IBUFG CLOCK_IN ( 
.I(clock_in),  
.O(clock) 
); 
 
DCM DCM0 ( 
.CLKFB(clock_out),  
.CLKIN(clock),  
.DSSEN(low),  
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk0),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm0_locked), 
.PSDONE(),  
.STATUS() 
); 
 
 
BUFG CLK_BUF0( 
.O(clock_out),  
.I(clk0) 
); 
// synthesis attribute DLL_FREQUENCY_MODE of DCM0 is "LOW"  
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM0 is "TRUE"  
// synthesis attribute STARTUP_WAIT of DCM0 is "TRUE"  
// synthesis attribute DFS_FREQUENCY_MODE of DCM0 is "LOW"  
// synthesis attribute CLKFX_DIVIDE of DCM0 is "1"  
// synthesis attribute CLKFX_MULTIPLY of DCM0 is "1"  
// synthesis attribute CLK_FEEDBACK of DCM0 is "1X"  
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM0 is "FIXED"  
// synthesis attribute PHASE_SHIFT of DCM0 is "0" 
 
DCM DCM1 ( 
.CLKFB(clock_with_ps_out),  
.CLKIN(clock),  
.DSSEN(low), 
.PSCLK(low),  
.PSEN(low),  
.PSINCDEC(low),  
.RST(low), 
.CLK0(clk1),  
.CLK90(),  
.CLK180(),  
.CLK270(),  
.CLK2X(),  
.CLK2X180(), 
.CLKDV(),  
.CLKFX(),  
.CLKFX180(),  
.LOCKED(dcm1_locked), 
.PSDONE(),  
.STATUS() 
); 
// synthesis attribute DLL_FREQUENCY_MODE of DCM1 is "LOW"  
// synthesis attribute DUTY_CYCLE_CORRECTION of DCM1 is "TRUE"  
// synthesis attribute STARTUP_WAIT of DCM1 is "TRUE"  
// synthesis attribute DFS_FREQUENCY_MODE of DCM1 is "LOW"  
// synthesis attribute CLKFX_DIVIDE of DCM1 is "1"  
// synthesis attribute CLKFX_MULTIPLY of DCM1 is "1"  
// synthesis attribute CLK_FEEDBACK of DCM1 is "1X"  
// synthesis attribute CLKOUT_PHASE_SHIFT of DCM1 is "FIXED"  
// synthesis attribute PHASE_SHIFT of DCM1 is "0" 
 
BUFG CLK_BUF1( 
.O(clock_with_ps_out),  
.I(clk1) 
); 
 
//synthesis translate_off 
defparam DCM0.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM0.STARTUP_WAIT = "TRUE"; 
defparam DCM0.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM0.CLKFX_DIVIDE = 1; 
defparam DCM0.CLKFX_MULTIPLY = 1; 
defparam DCM0.CLK_FEEDBACK = "1X"; 
defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE"; 
defparam DCM0.PHASE_SHIFT = "0"; 
 
defparam DCM1.DLL_FREQUENCY_MODE = "LOW"; 
defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE"; 
defparam DCM1.STARTUP_WAIT = "TRUE"; 
defparam DCM1.DFS_FREQUENCY_MODE = "LOW"; 
defparam DCM1.CLKFX_DIVIDE = 1; 
defparam DCM1.CLKFX_MULTIPLY = 1; 
defparam DCM1.CLK_FEEDBACK = "1X"; 
defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED"; 
defparam DCM1.PHASE_SHIFT = "0"; 
//synthesis translate_on 
 
endmodule // DCM_TOP