Creating FPGA Programming Files

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After the design has been completely routed, you must configure the device so that it can execute the desired function. Xilinx's bitstream generation program, BitGen, takes a fully routed NCD (Native Circuit Description) file as its input and produces a configuration bitstream--a binary file with a .bit extension.

The BIT file contains all of the configuration information from the NCD file defining the internal logic and interconnections of the FPGA, plus device-specific information from other files associated with the target device. The binary data in the BIT file can then be downloaded into the FPGA's memory cells, or it can be used to create a PROM file.

To create a configuration bitstream file:

1. Click the top-level source for the project in the Sources in Project window.
2. Click Generate Programming File in the Processes for Current Source window.
3. Click Process Run in the Project Navigator menu.

The programming file creation process runs. If there are no errors, the top_source_name.bit file is created.

4. To view the Programming File Report in the report window, double-click View Programming File Generation Report in the Processes for Current Source window.

The Programming File Report contains information about the BitGen run.

For a complete description of BitGen, see the Development System Reference Guide.

Launching Programming Tools

Select a programming tool to configure the target device. See the "Device Programming Tools" section below for a short overview of each tool.

To launch a programming tool:

1. Click the top-level source file in the Sources in Project window.
2. Double-click the programming tool name in the Processes for Current Source window.

The selected programming tool opens in its own window with the bitstream file loaded.

Setting FPGA Programming File Creation Options

You can set before programming file creation options before creating the programming file. To open the Process Properties dialog box containing these options:

1. Click the top-level design source file in the Sources in Project window for a project that targets an FPGA device.
2. Right-click Generate Programming File in the Processes for Current Source window.
3. Click Properties from the pull-down menu.

The Process Properties dialog box for the Generate Programming File process appears.

4. Click the tab for the options you want to set. You can set properties for the following options:
   • General Options
   • Configuration Options
   • Startup Options
   • Readback Options

These options are described in detail in the Project Navigator online help.

Note You can specify whether to display the Standard or Advanced list of properties in the Process Properties dialog boxes.