Generating CPLD Programming Files

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At the end of a successful CPLD implementation, a design database file (top_source_name.vm6) is created. From this, a JEDEC programming file can be generated. The iMPACT configuration tool uses this JED file to configure XC9500/XL/XV and XPLA3 (Coolrunner) CPLD devices.

Note For more information, see CPLD Design Flow Tutorials, accessible from the Project Navigator online help.

To create a JED programming file:

1. Click the top-level source for the project in the Sources in Project window.
2. Click Generate Programming File in the Processes for Current Source window.
3. Click Process Run in the Project Navigator menu.

The programming file creation process runs. If there are no errors, the top_source_name.jed file is created.

Setting CPLD Programming File Creation Options

This section describes the programming options you can set before creating the programming file. To open the Process Properties dialog box containing these options:

1. Click the top-level design source file in the Sources in Project window for a project that targets a CPLD device.
2. Right-click Generate Programming File in the Processes for Current Source window.
3. Click Properties from the pull-down menu.
4. The Process Properties dialog box for the Generate Programming File process appears.

You can set the following options for CPLD programming file creation:

• Signature/User Code

Values: Blank (default) / Four-character text string

Enters a unique text string in the Value field to identify the configuration data. You can enter a string of up to four alphanumeric characters. The device programmer can read the signature, and the person running the device programmer can verify that the correct configuration data file is loaded. Use the iMPACT configuration tool to identify the configuration data signature (usercode) of a programmed XC9500 or XC9500XL device. The default is to use the top_source_name.

• Jedec Test Vector File

Includes a TMV file in your JEDEC file. The TMV file is a test vector file generated when ABEL compiles a design containing user test vectors.

• Disable BUSHOLD Circuitry (9500XL/XV Only)
  Disables bus-hold keepers for all device I/Os.