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PIN (Modular Design Constraint)
PIN Description
The PIN constraint in conjunction with LOC defines a net location.
The PIN/LOC UCF constraint has the following syntax:
PIN "module.pin" LOC="location";
This UCF constraint is only used within the modular design flow. This UCF constraint is translated into a COMP/LOCATE constraint in the PCF file. This constraint has the following syntax in the PCF file:
COMP "name" LOCATE = SITE "location";
This constraint specifies that the pseudo component that will be created for the pin on the module should be located in the site location. Pseudo logic is only created when a net connects from a pin on one module to a pin on another module.
PIN Architecture Support
Virtex Yes Virtex-E Yes Spartan-II Yes Spartan-IIE Yes Spartan-3 Yes Virtex-II Yes Virtex-II Pro Yes Virtex-II Pro X Yes XC9500, XC9500XL, XC9500XV No CoolRunner XPLA3 No CoolRunner-II No
PIN Applicable Elements
Nets
PIN Propagation Rules
Not applicable.
PIN Syntax Examples
ECS Schematic Editor
Not applicable.
VHDL
Not applicable.
Verilog
Not applicable.
ABEL
Not applicable.
NCF
Not applicable.
UCF
PIN “module.pin” LOC=location;
XCF
Not applicable.
Old XST Constraint File
Not applicable.
Constraints Editor
Not applicable.
PCF
Not applicable.
Floorplanner
Not applicable.
PACE
Not applicable.
FPGA Editor
Not applicable.
XST Command Line
Not applicable.
Project Navigator
Not applicable.
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