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PLD_CE
PLD_CE Description
PLD_CE is a synthesis constraint. It specifies how sequential logic should be implemented when it contains a clock enable, either using the specific device resources available for that or generating equivalent logic.
This option allows you to specify the way the clock enable function will be implemented if presented in the design. Two values are available:
Keeping or not keeping the clock enable signal depends on the design logic. Sometimes, when the clock enable is the result of a Boolean expression, saying NO with this option may improve the fitting result because the input data of the flip-flop is simplified when it is merged with the clock enable expression.
PLD_CE Architecture Support
PLD_CE Applicable Elements
PLD_CE can be applied globally only.
PLD_CE Propagation Rules
Not applicable.
PLD_CE Syntax Examples
ECS Schematic Editor
Not applicable.
VHDL
Not applicable.
Verilog
Not applicable.
ABEL
Not applicable.
NCF
Not applicable.
UCF
Not applicable.
XCF
Not applicable.
Old XST Constraint File
Not applicable.
Constraints Editor
Not applicable.
PCF
Not applicable.
Floorplanner
Not applicable.
PACE
Not applicable.
FPGA Editor
Not applicable.
XST Command Line
Define globally with the -pld_ce command line option of the run command. Following is the basic syntax:
-pld_ce {YES|NO}
The default is YES.
See the "Command Line Mode" chapter in the XST User Guide for details.
Project Navigator
You can define PLD_CE globally with the Clock Enable option in the Xilinx Specific Options tab of the Process Properties dialog box within the Project Navigator.
With a design selected in the Sources window, right-click Synthesize in the Processes window to access the appropriate Process Properties dialog box.
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