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PLD_MP
PLD_MP Description
PLD_MP is a synthesis constraint. It is useful for making the macro handling independent of design hierarchy processing (see Flatten Hierarchy option). This allows you to merge all hierarchical blocks in the top module, while still keeping the macros as hierarchical modules. You can also keep the design hierarchy except for the macros, which are merged with the surrounded logic. Merging the macros sometimes gives better results for design fitting. Two values are available for this option:
Depending on the Flatten Hierarchy value, a rejected macro becomes a hierarchical block (Flatten Hierarchy=no) or is merged in the design logic (Flatten Hierarchy=yes). Very small macros (2-bit adders, 4-bit multiplexers) are always merged, independent of the Macro Preserve or Flatten Hierarchy options.
PLD_MP Architecture Support
PLD_MP is supported with all CPLDs.
PLD_MP Applicable Elements
You can apply PLD_MP globally only.
PLD_MP Propagation Rules
Not applicable.
PLD_MP Syntax Examples
ECS Schematic Editor
Not applicable.
VHDL
Not applicable.
Verilog
Not applicable.
ABEL
Not applicable.
NCF
Not applicable.
UCF
Not applicable.
XCF
Not applicable.
Old XST Constraint File
Not applicable.
Constraints Editor
Not applicable.
PCF
Not applicable.
Floorplanner
Not applicable.
PACE
Not applicable.
FPGA Editor
Not applicable.
XST Command Line
Define globally with the -pld_mp command line option of the run command. Following is the basic syntax:
-pld_mp {YES|NO}
The default is YES.
See the "Command Line Mode" chapter in the XST User Guide for details.
Project Navigator
You can define PLD_MP globally with the Macro Preserve option in the Xilinx Specific Options tab of the Process Properties dialog box within the Project Navigator.
With a design selected in the Sources window, right-click Synthesize in the Processes window to access the appropriate Process Properties dialog box.
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