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REGISTER_POWERUP
REGISTER_POWERUP Description
XST will not automatically figure out and enforce register power-up values. You must explicitly specify them if needed with REGISTER_POWERUP. This XST synthesis constraint can be assigned to a VHDL enumerated type, or it may be directly attached to a VHDL signal or a Verilog register node through a VHDL attribute or Verilog meta comment. The constraint value may be a binary string or a symbolic code value.
REGISTER_POWERUP Architecture Support
REGISTER_POWERUP Applicable Elements
Signals and types
REGISTER_POWERUP Propagation Rules
Applies to the signal or type to which it is attached.
REGISTER_POWERUP Syntax Examples
ECS Schematic Editor
Not applicable.
VHDL
Following are some examples of REGISTER_POWERUP.
Example 1
The register is defined with a predefined VHDL type such as std_logic_vector. The constraint value is necessarily a binary code.
signal myreg : std_logic_vector (3 downto 0);
attribute register_powerup of myreg : signal is "0001";
Example 2
The register is defined with an enumerated type (symbolic state machine). The constraint is attached to the signal and its value is one of the symbolic states defined. Actual power-up code will differ depending on the way the state machine is encoded.
type state_type is (s1, s2, s3, s4, s5);
signal state1 : state_type;
attribute register_powerup of state1 : signal is "s2";
Example 3
The constraint is attached to an enumerated type. All registers defined with that type inherit the constraint.
type state_type is (s1, s2, s3, s4, s5);
attribute register_powerup of state_type : type is "s1";
signal state1, state2 : state_type;
Example 4
For enumerated type objects, the power-up value may also be defined as a binary code. However, if automatic encoding is enabled and leads to a different encoding scheme (in particular a different code width), the power-up value will be ignored.
type state_type is (s1, s2, s3, s4, s5);
attribute enum_encoding of state_type : type is "001 011 010 100 111";
attribute register_powerup of state_type : type is "100";
signal state1 : state_type;
For a more detailed discussion of the basic VHDL syntax, see the "VHDL" section of the "Constraint Entry" chapter.
Verilog
Not applicable.
ABEL
Not applicable.
NCF
Not applicable.
UCF
Not applicable.
XCF
BEGIN MODEL “entity_name”
NET “signal_name” register_powerup=”string”;
END;
Old XST Constraint File
No attribute declaration is required. An attribute can be directly specified using the following syntax:
attribute register_powerup of state_type type is "001 011 010 100 111";
For more details, see the "Old XST Constraint File" section of the “Constraint Entry” chapter.
Constraints Editor
Not applicable.
PCF
Not applicable.
Floorplanner
Not applicable.
PACE
Not applicable.
FPGA Editor
Not applicable.
XST Command Line
Example 1
attribute register_powerup of myreg : signal is "0001";
Example 2
attribute register_powerup of state1 : signal is "s2";
Example 3
attribute register_powerup of state1 : signal is "s2";
attribute register_powerup of state2 : signal is "s2";
Example 4
attribute register_powerup of state1 : signal is "100";
Project Navigator
Not applicable.
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