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RAMB4_Sm_Sn

4096-Bit Dual-Port Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 8, or 16 Bits

Spartan-II,
Spartan-IIE
Spartan-3
Virtex,
Virtex-E
Virtex-II,
Virtex-II Pro,
Virtex-II Pro X
XC9500/XV/XL
CoolRunner
XPLA3
CoolRunner-II
Primitive
N/A
Primitive
N/A
N/A
N/A
N/A

RAMB4_Sm_Sn Representations

The RAMB4_Sm_Sn components listed in the following table are 4096-bit dual-ported dedicated random access memory blocks with synchronous write capability. Each port is independent of the other while accessing the same set of 4096 memory cells. Each port is independently configured to a specific data width.

Component
Port A
Depth
Port A
Width
Port A
ADDR
Port A
DI
Port B
Depth
Port B
Width
Port B
ADDR
Port B
DI
RAMB4_S1_S1
4096
1
(11:0)
(0:0)
4096
1
(11:0)
(0:0)
RAMB4_S1_S2
4096
1
(11:0)
(0:0)
2048
2
(10:0)
(1:0)
RAMB4_S1_S4
4096
1
(11:0)
(0:0)
1024
4
(9:0)
(3:0)
RAMB4_S1_S8
4096
1
(11:0)
(0:0)
512
8
(8:0)
(7:0)
RAMB4_S1_S16
4096
1
(11:0)
(0:0)
256
16
(7:0)
(15:0)
RAMB4_S2_S2
2048
2
(10:0)
(1:0)
2048
2
(10:0)
(1:0)
RAMB4_S2_S4
2048
2
(10:0)
(1:0)
1024
4
(9:0)
(3:0)
RAMB4_S2_S8
2048
2
(10:0)
(1:0)
512
8
(8:0)
(7:0)
RAMB4_S2_S16
2048
2
(10:0)
(1:0)
256
16
(7:0)
(15:0)
RAMB4_S4_S4
1024
4
(9:0)
(3:0)
1024
4
(9:0)
(3:0)
RAMB4_S4_S8
1024
4
(9:0)
(3:0)
512
8
(8:0)
(7:0)
RAMB4_S4_S16
1024
4
(9:0)
(3:0)
256
16
(7:0)
(15:0)
RAMB4_S8_S8
512
8
(8:0)
(7:0)
512
8
(8:0)
(7:0)
RAMB4_S8_S16
512
8
(8:0)
(7:0)
256
16
(7:0)
(15:0)
RAMB4_S16_S16
256
16
(7:0)
(15:0)
256
16
(7:0)
(15:0)
ADDR=address bus for the port
DI=data input bus for the port

Each port is fully synchronous with independent clock pins. All port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All port B input pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the CLKB.

The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and the output (DOA) retains the last state. When ENA is High and reset (RSTA) is High, DOA is cleared during the Low-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data at DIA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during the Low-to-High clock transition. When ENA and WEA are High, the data on the data input (DIA) is loaded into the word selected by the write address (ADDRA) during the Low-to-High clock transition and the data output (DOA) reflects the selected (addressed) word.

The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and the output (DOB) retains the last state. When ENB is High and reset (RSTB) is High, DOB is cleared during the Low-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data at DIB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during the Low-to-High clock transition. When ENB and WEB are High, the data on the data input (DIB) is loaded into the word selected by the write address (ADDRB) during the Low-to-High clock transition and the data output (DOB) reflects the selected (addressed) word.

The above descriptions assume active High control pins (ENA, WEA, RSTA, CLKA, ENB, WEB, RSTB, and CLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB4 port is absorbed into the block and does not use a CLB resource.

RAMB_Sm_Sn's may be initialized during configuration. See the following truth table.

Block RAM output registers are asynchronously cleared, output Low, when power is applied. The initial contents of the block RAM are not altered.

Virtex, Virtex-E, Spartan-II, and Spartan-IIE simulate power-on when global set/reset (GSR) is active.

GSR defaults to active-High but can be inverted by adding an inverter in front of the GSR input of the STARTUP_SPARTAN2, STARTUP_SPARTAN3, STARTUP_VIRTEX, or STARTUP_VIRTEX2 symbol.

Mode selection is shown in the following truth table.

Inputs
Outputs
EN(A/B)
RST(A/B)
WE(A/B)
CLK(A/B)
ADDR(A/B)
DI(A/B)
DO(A/B)
RAM Contents
0
X
X
X
X
X
No Chg
No Chg
1
1
0
X
X
0
No Chg
1
1
1
addr
data
0
RAM(addr) =>data
1
0
0
addr
X
RAM(addr)
No Chg
1
0
1
addr
data
data
RAM(addr) =>data
addr=RAM address of port A/B
RAM(addr)=RAM contents at address ADDRA/ADDRB
data=RAM input data at pins DIA/DIB

Address Mapping

Each port accesses the same set of 4096 memory cells using an addressing scheme that is dependent on the width of the port. The physical RAM location that is addressed for a particular width is determined from the following formula.

   Start=((ADDR port+1)*(Widthport)) -1
   End=(ADDRport)*(Widthport)

The following table shows address mapping for each port width.

Port Address Mapping
Port Width
Port Addresses
1
4096
<-----
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
2
2048
<-----
07
06
05
04
03
02
01
00
4
1024
<-----
03
02
01
00
8
512
<-----
01
00
16
256
<-----
00

Port A and Port B Conflict Resolution

A RAMB4_Sm_Sn component is a true dual-ported RAM in that it allows simultaneous reads of the same memory cell. When one port is performing a write to a given memory cell, the other port should not address that memory cell (for a write or a read) within the clock-to-clock setup window.

If both ports write to the same memory cell simultaneously, violating the clock-to-setup requirement, the data stored will be invalid.

If one port attempts to read from the same memory cell that the other is simultaneously writing to, violating the clock setup requirement, the write will be successful but the data read will be invalid.

Specifying Initial Contents of a Block RAM

You can use the INIT_0x attributes to specify an initial value during device configuration. The initialization of each RAMB4_Sm_Sn is set by 16 initialization attributes (INIT_00 through INIT_0F) of 64 hex values for a total of 4096 bits. See the INIT_xx section of the Constraints Guide for more information on these attributes.

If any INIT_0x attribute is not specified, it is configured as zeros. Partial initialization strings are padded with zeros to the left.

Usage

For HDL, this design element can be inferred or instantiated. The instantiation code is shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB4_Sm_Sn

-- Component Declaration for RAMB4_Sm_Sn
-- Should be placed after architecture statement but before begin keyword
component RAMB4_Sm_Sn
-- synthesis translate_off
generic (
       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
);
-- synthesis translate_on
   port (DOA : out STD_LOGIC_VECTOR (0 downto 0);
         DOB : out STD_LOGIC_VECTOR (0 downto 0);
         ADDRA : in STD_LOGIC_VECTOR (11 downto 0);
         ADDRB : in STD_LOGIC_VECTOR (11 downto 0);
         CLKA : in STD_ULOGIC;
         CLKB : in STD_ULOGIC;
         DIA : in STD_LOGIC_VECTOR (0 downto 0);
         DIB : in STD_LOGIC_VECTOR (0 downto 0);
         ENA : in STD_ULOGIC;
         ENB : in STD_ULOGIC;
         RSTA : in STD_ULOGIC;
         RSTB : in STD_ULOGIC;
         WEA : in STD_ULOGIC;
         WEB : in STD_ULOGIC);
end component;
-- Component Attribute Specification for RAMB4_Sm_Sn
-- Should be placed after architecture declaration but before the begin keyword
-- Put attributes, if necessary
-- Component Instantiation for RAMB4_Sm_Sn
-- Should be placed in architecture after the begin keyword
RAMB4_Sm_Sn_INSTANCE_NAME : RAMB4_Sm_Sn
-- synthesis translate_off
generic map (
INIT_00 => vector_value,
INIT_01 => vector_value,
INIT_02 => vector_value,
INIT_03 => vector_value,
INIT_04 => vector_value,
INIT_05 => vector_value,
INIT_06 => vector_value,
INIT_07 => vector_value,
INIT_08 => vector_value,
INIT_09 => vector_value,
INIT_0A => vector_value,
INIT_0B => vector_value,
INIT_0C => vector_value,
INIT_0D => vector_value,
INIT_0E => vector_value,
INIT_0F => vector_value)
   -- synopsys translate_on
   port map (DOA => user_DOA,
             DOB => user_DOB,
             ADDRA => user_ADDRA,
             ADDRB => user_ADDRB,
             CLKA => user_CLKA,
             CLKB => user_CLKB,
             DIA => user_DIA,
             DIB => user_DIB,
             ENA => user_ENA,
             ENB => user_ENB,
             RSTA => user_RSTA,
             RSTB => user_RSTB,
             WEA => user_WEA,
             WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S1, S2, and S4

RAMB4_Sm_Sn user_instance_name (.DOA (user_DOA),
                                .DOB (user_DOB),
                                .ADDRA (user_ADDRA),
                                .ADDRB (user_ADDRB),
                                .CLKA (user_CLKA),
                                .CLKB (user_CLKB),
                                .DIA (user_DIA),
                                .DIB (user_DIB),
                                .ENA (user_ENA),
                                .ENB (user_ENB),
                                .RSTA (user_RSTA),
                                .RSTB (user_RSTB),
                                .WEA (user_WEA),
                                .WEB (user_WEB));
defparam user_instance_name.INIT_00 = 256_bit_hex_value;
defparam user_instance_name.INIT_01 = 256_bit_hex_value;
defparam user_instance_name.INIT_02 = 256_bit_hex_value;
defparam user_instance_name.INIT_03 = 256_bit_hex_value;
defparam user_instance_name.INIT_04 = 256_bit_hex_value;
defparam user_instance_name.INIT_05 = 256_bit_hex_value;
defparam user_instance_name.INIT_06 = 256_bit_hex_value;
defparam user_instance_name.INIT_07 = 256_bit_hex_value;
defparam user_instance_name.INIT_08 = 256_bit_hex_value;
defparam user_instance_name.INIT_09 = 256_bit_hex_value;
defparam user_instance_name.INIT_0A = 256_bit_hex_value;
defparam user_instance_name.INIT_0B = 256_bit_hex_value;
defparam user_instance_name.INIT_0C = 256_bit_hex_value;
defparam user_instance_name.INIT_0D = 256_bit_hex_value;
defparam user_instance_name.INIT_0E = 256_bit_hex_value;
defparam user_instance_name.INIT_0F = 256_bit_hex_value;

Commonly Used Constraints

INIT_xx

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