RAMB16

RAMB16_Sn

16384-Bit Data Memory and 2048-Bit Parity Memory, Single-Port Synchronous Block RAM with Port Width (n) Configured to 1, 2, 4, 9, 18, or 36 Bits

Spartan-II,

Spartan-IIE

Spartan-3

Virtex,

Virtex-E

Virtex-II,

Virtex-II Pro,
Virtex-II Pro X

XC9500/XV/XL

CoolRunner

XPLA3

CoolRunner-II

N/A

Primitive

N/A

Primitive

N/A

N/A

N/A

RAMB16_S1 through RAMB16_S36 Representations

RAMB16_S1, RAMB16_S2, RAMB16_S4, RAMB16_S9, RAMB16_S18, and RAMB16_S36 are dedicated random access memory blocks with synchronous write capability. The block RAM port has 16384 bits of data memory. RAMB16_S9, RAMB16_S18, and RAMB16_S36 have an additional 2048 bits of parity memory. The RAMB16_Sn cell configurations are listed in the following table.

Component

Data Cells

Parity Cells

Address Bus

Data Bus

Parity Bus

Depth

Width

Depth

Width

RAMB16_S1

16384

1

-

-

(13:0)

(0:0)

-

RAMB16_S2

8192

2

-

-

(12:0)

(1:0)

-

RAMB16_S4

4096

4

-

-

(11:0)

(3:0)

-

RAMB16_S9

2048

8

2048

1

(10:0)

(7:0)

(0:0)

RAMB16_S18

1024

16

1024

2

(9:0)

(15:0)

(1:0)

RAMB16_S36

512

32

512

4

(8:0)

(31:0)

(3:0)

The enable (EN) pin controls read, write, and reset. When EN is Low, no data is written and the outputs (DO and DOP) retain the last state. When EN is High and reset (SSR) is High, DO and DOP are set to SRVAL during the Low-to-High clock (CLK) transition; if write enable (WE) is High, the memory contents reflect the data at DI and DIP. When SSR is Low, EN is High, and WE is Low, the data stored in the RAM address (ADDR) is read during the Low-to-High clock transition. The output value depends on the mode. By default WRITE_MODE=WRITE_FIRST, when EN and WE are High and SSR is Low, the data on the data inputs (DI and DIP) is loaded into the word selected by the write address (ADDR) during the Low-to-High clock transition. See “Write Mode Selection” for information on setting the WRITE_MODE.

The above description assumes an active High EN, WE, SSR, and CLK. However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB16 port is absorbed into the block and does not use a CLB resource.

Inputs

Outputs

GSR

EN

SSR

WE

CLK

ADDR

DI

DIP

DO

DOP

RAM Contents

Data RAM

Parity RAM

1

X

X

X

X

X

X

X

INIT

INIT

No Chg

No Chg

0

0

X

X

X

X

X

X

No Chg

No Chg

No Chg

No Chg

0

1

1

0

X

X

X

SRVAL

SRVAL

No Chg

No Chg

0

1

1

1

addr

data

pdata

SRVAL

SRVAL

RAM(addr) =>data

RAM(addr) =>pdata

0

1

0

0

addr

X

X

RAM(addr)

RAM(addr)

No Chg

No Chg

0

1

0

1

addr

data

pdata

No Chga
RAM (addr)b
datac

No Chga
RAM(addr)b
pdatac

RAM(addr) =>data

RAM(addr) =>pdata

GSR=Global Set Reset signal

INIT=Value specified by the INIT attribute for data memory. Default is all zeros.
SRVAL=Value after assertion of SSR as specified by the SRVAL attribute.

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data

pdata=RAM parity data

aWRITE_MODE=NO_CHANGE

bWRITE_MODE=READ_FIRST

cWRITE_MODE=WRITE_FIRST

Initializing Memory Contents of a Single-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory contents of a RAMB16 during device configuration. The initialization of each RAMB16_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64 hex values for a total of 16384 bits.

You can use the INITP_xx attributes to specify an initial value for the parity memory during device configuration or assertion. The initialization of the parity memory for ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00 through INITP_07) of 64 hex values for a total of 2048 bits.

If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial strings are padded with zeros to the left.

See the Constraints Guide for more information on these attributes.

Initializing the Output Register of a Single-Port RAMB16

In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, each bit in the output register can be initialized at power on to either a 0 or 1. In addition, the initial state specified for power on can be different than the state that results from assertion of a set/reset. Two types of properties control initialization of the output register for a single-port RAMB16: INIT and SRVAL. The INIT attribute specifies the output register value at power on. You can use the SRVAL attribute to define the state resulting from assertion of the SSR (set/reset) input.

The INIT and SRVAL attributes specify the initialization value as a hexadecimal string. The value is dependent upon the port width. For example, for a RAMB16_S1 with port width equal to 1, the output register contains 1 bit. Therefore, the INIT or SRVAL value can only be specified as a 1 or 0. For RAMB16_S4 with port width equal to 4, the output register contains 4 bits. In this case, you can specify a hexadecimal value from 0 through F to initialize the 4 bits of the output register.

For those ports that include parity bits, the parity portion of the output register is specified in the high order bit position of the INIT or SRVAL value.

The INIT and SRVAL attributes default to zero if they are not set by the user.

See the Constraints Guide for more information on these attributes.

Write Mode Selection

The WRITE_MODE attribute controls RAMB16 memory and output contents. By default, the WRITE_MODE is set to WRITE_FIRST. This means that input is read, written to memory, and then passed to output. You can set the WRITE_MODE to READ_FIRST to read the memory contents, pass the memory contents to the outputs, and then write the input to memory. Or, you can set the WRITE_MODE to NO_CHANGE to have the input written to memory without changing the output.

Usage

For HDL, this design element can be inferred or instantiated. The instantiation code is shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB16_S1, S2, and S4

-- Component Declaration for RAMB16_{S1 | S2 | S4}

-- Should be placed after architecture statement but before begin keyword

component RAMB16_{S1 | S2 | S4}

-- synthesis translate_off

generic (

       INIT : bit_vector := X"0";

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       SRVAL : bit_vector := X"0";

       WRITE_MODE : string := "WRITE_FIRST");

   -- synthesis translate_on

   port (DO : out STD_LOGIC_VECTOR (0 downto 0)

         ADDR : in STD_LOGIC_VECTOR (13 downto 0);

         CLK : in STD_ULOGIC;

         DI : in STD_LOGIC_VECTOR (0 downto 0);

         EN : in STD_ULOGIC;

         SSR : in STD_ULOGIC;

         WE : in STD_ULOGIC);

end component;

-- Component Attribute Specification for RAMB16_{S1 | S2 | S4}

-- Should be placed after architecture declaration but before the begin keyword

-- Put attributes, if necessary

-- Component Instantiation for RAMB16_{S1 | S2 | S4}

-- Should be placed in architecture after the begin keyword

RAMB16_{S1 | S2 | S4}_INSTANCE_NAME : RAMB16_S1

-- synthesis translate_off

generic map (

INIT => bit_value,

       INIT_00 => vector_value,

INIT_01 => vector_value,

INIT_02 => vector_value,

INIT_03 => vector_value,

INIT_04 => vector_value,

INIT_05 => vector_value,

INIT_06 => vector_value,

INIT_07 => vector_value,

INIT_08 => vector_value,

INIT_09 => vector_value,

INIT_0A => vector_value,

INIT_0B => vector_value,

INIT_0C => vector_value,

INIT_0D => vector_value,

INIT_0E => vector_value,

INIT_0F => vector_value,

INIT_10 => vector_value,

INIT_11 => vector_value,

INIT_12 => vector_value,

INIT_13 => vector_value,

INIT_14 => vector_value,

INIT_15 => vector_value,

INIT_16 => vector_value,

INIT_17 => vector_value,

INIT_18 => vector_value,

INIT_19 => vector_value,

INIT_1A => vector_value,

INIT_1B => vector_value,

INIT_1C => vector_value,

INIT_1D => vector_value,

INIT_1E => vector_value,

INIT_1F => vector_value,

INIT_20 => vector_value,

INIT_21 => vector_value,

INIT_22 => vector_value,

INIT_23 => vector_value,

INIT_24 => vector_value,

INIT_25 => vector_value,

INIT_26 => vector_value,

INIT_27 => vector_value,

INIT_28 => vector_value,

INIT_29 => vector_value,

INIT_2A => vector_value,

INIT_2B => vector_value,

INIT_2C => vector_value,

INIT_2D => vector_value,

INIT_2E => vector_value,

INIT_2F => vector_value,

INIT_30 => vector_value,

INIT_31 => vector_value,

INIT_32 => vector_value,

INIT_33 => vector_value,

INIT_34 => vector_value,

INIT_35 => vector_value,

INIT_36 => vector_value,

INIT_37 => vector_value,

INIT_38 => vector_value,

INIT_39 => vector_value,

INIT_3A => vector_value,

INIT_3B => vector_value,

INIT_3C => vector_value,

INIT_3D => vector_value,

INIT_3E => vector_value,

INIT_3F => vector_value,

       SRVAL=> bit_value,

       WRITE_MODE => user_WRITE_MODE)

   -- synopsys translate_on

   port map (DO => user_DO,

             ADDR => user_ADDR,

             CLK => user_CLK,

             DI => user_DI,

             EN => user_EN,

             SSR => user_SSR,

             WE => user_WE);

Verilog Instantiation Template for RAMB16_S1, S2, and S4

RAMB16_{S1 | S2 | S4} user_instance_name (.DO(user_DO),

                                          .ADDR (user_ADDR),

                                          .CLK (user_CLK),

                                          .DI (user_DI),

                                          .EN (user_EN),

                                          .SSR (user_SSR),

                                          .WE (user_WE));

defparam user_instance_name.INIT = bit_value;

defparam user_instance_name.INIT_00 = 256_bit_hex_value;

defparam user_instance_name.INIT_01 = 256_bit_hex_value;

defparam user_instance_name.INIT_02 = 256_bit_hex_value;

defparam user_instance_name.INIT_03 = 256_bit_hex_value;

defparam user_instance_name.INIT_04 = 256_bit_hex_value;

defparam user_instance_name.INIT_05 = 256_bit_hex_value;

defparam user_instance_name.INIT_06 = 256_bit_hex_value;

defparam user_instance_name.INIT_07 = 256_bit_hex_value;

defparam user_instance_name.INIT_08 = 256_bit_hex_value;

defparam user_instance_name.INIT_09 = 256_bit_hex_value;

defparam user_instance_name.INIT_0A = 256_bit_hex_value;

defparam user_instance_name.INIT_0B = 256_bit_hex_value;

defparam user_instance_name.INIT_0C = 256_bit_hex_value;

defparam user_instance_name.INIT_0D = 256_bit_hex_value;

defparam user_instance_name.INIT_0E = 256_bit_hex_value;

defparam user_instance_name.INIT_0F = 256_bit_hex_value;

defparam user_instance_name.INIT_10 = 256_bit_hex_value;

defparam user_instance_name.INIT_11 = 256_bit_hex_value;

defparam user_instance_name.INIT_12 = 256_bit_hex_value;

defparam user_instance_name.INIT_13 = 256_bit_hex_value;

defparam user_instance_name.INIT_14 = 256_bit_hex_value;

defparam user_instance_name.INIT_15 = 256_bit_hex_value;

defparam user_instance_name.INIT_16 = 256_bit_hex_value;

defparam user_instance_name.INIT_17 = 256_bit_hex_value;

defparam user_instance_name.INIT_18 = 256_bit_hex_value;

defparam user_instance_name.INIT_19 = 256_bit_hex_value;

defparam user_instance_name.INIT_1A = 256_bit_hex_value;

defparam user_instance_name.INIT_1B = 256_bit_hex_value;

defparam user_instance_name.INIT_1C = 256_bit_hex_value;

defparam user_instance_name.INIT_1D = 256_bit_hex_value;

defparam user_instance_name.INIT_1E = 256_bit_hex_value;

defparam user_instance_name.INIT_1F = 256_bit_hex_value;

defparam user_instance_name.INIT_20 = 256_bit_hex_value;

defparam user_instance_name.INIT_21 = 256_bit_hex_value;

defparam user_instance_name.INIT_22 = 256_bit_hex_value;

defparam user_instance_name.INIT_23 = 256_bit_hex_value;

defparam user_instance_name.INIT_24 = 256_bit_hex_value;

defparam user_instance_name.INIT_25 = 256_bit_hex_value;

defparam user_instance_name.INIT_26 = 256_bit_hex_value;

defparam user_instance_name.INIT_27 = 256_bit_hex_value;

defparam user_instance_name.INIT_28 = 256_bit_hex_value;

defparam user_instance_name.INIT_29 = 256_bit_hex_value;

defparam user_instance_name.INIT_2A = 256_bit_hex_value;

defparam user_instance_name.INIT_2B = 256_bit_hex_value;

defparam user_instance_name.INIT_2C = 256_bit_hex_value;

defparam user_instance_name.INIT_2D = 256_bit_hex_value;

defparam user_instance_name.INIT_2E = 256_bit_hex_value;

defparam user_instance_name.INIT_2F = 256_bit_hex_value;

defparam user_instance_name.INIT_30 = 256_bit_hex_value;

defparam user_instance_name.INIT_31 = 256_bit_hex_value;

defparam user_instance_name.INIT_32 = 256_bit_hex_value;

defparam user_instance_name.INIT_33 = 256_bit_hex_value;

defparam user_instance_name.INIT_34 = 256_bit_hex_value;

defparam user_instance_name.INIT_35 = 256_bit_hex_value;

defparam user_instance_name.INIT_36 = 256_bit_hex_value;

defparam user_instance_name.INIT_37 = 256_bit_hex_value;

defparam user_instance_name.INIT_38 = 256_bit_hex_value;

defparam user_instance_name.INIT_39 = 256_bit_hex_value;

defparam user_instance_name.INIT_3A = 256_bit_hex_value;

defparam user_instance_name.INIT_3B = 256_bit_hex_value;

defparam user_instance_name.INIT_3C = 256_bit_hex_value;

defparam user_instance_name.INIT_3D = 256_bit_hex_value;

defparam user_instance_name.INIT_3E = 256_bit_hex_value;

defparam user_instance_name.INIT_3F = 256_bit_hex_value;

   defparam user_instance_name.SRVAL = bit_value;

defparam user_instance_name.WRITE_MODE = write_mode;

VHDL Instantiation Template for RAMB16_S9, S18 and S36

-- Component Declaration for RAMB16_{S9 | S18 | S36}

-- Should be placed after architecture statement but before begin keyword

component RAMB16_{S9 | S18 | S36}

-- synthesis translate_off

generic (

       INIT : bit_vector := X"0";

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       SRVAL : bit_vector := X"0";

       WRITE_MODE : string := "WRITE_FIRST";

);

-- synthesis translate_on

   port (DO : out STD_LOGIC_VECTOR (0 downto 0);

         DOP : out STD_LOGIC_VECTOR (1 downto 0);

         ADDR : in STD_LOGIC_VECTOR (13 downto 0);

         CLK : in STD_ULOGIC;

         DI : in STD_LOGIC_VECTOR (0 downto 0);

         DIP : in STD_LOGIC_VECTOR (0 downto 0);

         EN : in STD_ULOGIC;

         SSR : in STD_ULOGIC;

         WE : in STD_ULOGIC);

end component;

-- Component Attribute Specification for RAMB16_{S9 | S18 | S36}

-- Should be placed after architecture declaration but before the begin keyword

-- Put attributes, if necessary

-- Component Instantiation for RAMB16_{S9 | S18 | S36}

-- Should be placed in architecture after the begin keyword

RAMB16_{S9 | S18 | S36}_INSTANCE_NAME : RAMB16_S1

-- synthesis translate_off

generic map (

INIT => bit_value,

INIT_00 => vector_value,

INIT_01 => vector_value,

INIT_02 => vector_value,

INIT_03 => vector_value,

INIT_04 => vector_value,

INIT_05 => vector_value,

INIT_06 => vector_value,

INIT_07 => vector_value,

INIT_08 => vector_value,

INIT_09 => vector_value,

INIT_0A => vector_value,

INIT_0B => vector_value,

INIT_0C => vector_value,

INIT_0D => vector_value,

INIT_0E => vector_value,

INIT_0F => vector_value,

INIT_10 => vector_value,

INIT_11 => vector_value,

INIT_12 => vector_value,

INIT_13 => vector_value,

INIT_14 => vector_value,

INIT_15 => vector_value,

INIT_16 => vector_value,

INIT_17 => vector_value,

INIT_18 => vector_value,

INIT_19 => vector_value,

INIT_1A => vector_value,

INIT_1B => vector_value,

INIT_1C => vector_value,

INIT_1D => vector_value,

INIT_1E => vector_value,

INIT_1F => vector_value,

INIT_20 => vector_value,

INIT_21 => vector_value,

INIT_22 => vector_value,

INIT_23 => vector_value,

INIT_24 => vector_value,

INIT_25 => vector_value,

INIT_26 => vector_value,

INIT_27 => vector_value,

INIT_28 => vector_value,

INIT_29 => vector_value,

INIT_2A => vector_value,

INIT_2B => vector_value,

INIT_2C => vector_value,

INIT_2D => vector_value,

INIT_2E => vector_value,

INIT_2F => vector_value,

INIT_30 => vector_value,

INIT_31 => vector_value,

INIT_32 => vector_value,

INIT_33 => vector_value,

INIT_34 => vector_value,

INIT_35 => vector_value,

INIT_36 => vector_value,

INIT_37 => vector_value,

INIT_38 => vector_value,

INIT_39 => vector_value,

INIT_3A => vector_value,

INIT_3B => vector_value,

INIT_3C => vector_value,

INIT_3D => vector_value,

INIT_3E => vector_value,

INIT_3F => vector_value,

       INITP_00 => vector_value,

       INITP_01 => vector_value,

       INITP_02 => vector_value,

       INITP_03 => vector_value,

       INITP_04 => vector_value,

       INITP_05 => vector_value,

       INITP_06 => vector_value,

       INITP_07 => vector_value

       SRVAL => bit_value,

       WRITE_MODE => user_WRITE_MODE)

   -- synopsys translate_on

port map (DO => user_DO,

             DOP => user_DOP,

             ADDR => user_ADDR,

             CLK => user_CLK,

             DI => user_DI,

             DIP => user_DIP,

             EN => user_EN,

             SSR => user_SSR,

             WE => user_WE);

Verilog Instantiation Template for RAMB16_S18 and S36

RAMB16_{S9 | S18 | S36} user_instance_name (.DO(user_DO),

                                            .DOP (user_DOP),

                                            .ADDR (user_ADDR),

                                            .CLK (user_CLK),

                                            .DI (user_DI),

                                            .DIP (user_DIP),

                                            .EN (user_EN),

                                            .SSR (user_SSR),

                                            .WE (user_WE));

defparam user_instance_name.INIT = bit_value;

    defparam user_instance_name.INIT_00 = 256_bit_hex_value;

defparam user_instance_name.INIT_01 = 256_bit_hex_value;

defparam user_instance_name.INIT_02 = 256_bit_hex_value;

defparam user_instance_name.INIT_03 = 256_bit_hex_value;

defparam user_instance_name.INIT_04 = 256_bit_hex_value;

defparam user_instance_name.INIT_05 = 256_bit_hex_value;

defparam user_instance_name.INIT_06 = 256_bit_hex_value;

defparam user_instance_name.INIT_07 = 256_bit_hex_value;

defparam user_instance_name.INIT_08 = 256_bit_hex_value;

defparam user_instance_name.INIT_09 = 256_bit_hex_value;

defparam user_instance_name.INIT_0A = 256_bit_hex_value;

defparam user_instance_name.INIT_0B = 256_bit_hex_value;

defparam user_instance_name.INIT_0C = 256_bit_hex_value;

defparam user_instance_name.INIT_0D = 256_bit_hex_value;

defparam user_instance_name.INIT_0E = 256_bit_hex_value;

defparam user_instance_name.INIT_0F = 256_bit_hex_value;

defparam user_instance_name.INIT_10 = 256_bit_hex_value;

defparam user_instance_name.INIT_11 = 256_bit_hex_value;

defparam user_instance_name.INIT_12 = 256_bit_hex_value;

defparam user_instance_name.INIT_13 = 256_bit_hex_value;

defparam user_instance_name.INIT_14 = 256_bit_hex_value;

defparam user_instance_name.INIT_15 = 256_bit_hex_value;

defparam user_instance_name.INIT_16 = 256_bit_hex_value;

defparam user_instance_name.INIT_17 = 256_bit_hex_value;

defparam user_instance_name.INIT_18 = 256_bit_hex_value;

defparam user_instance_name.INIT_19 = 256_bit_hex_value;

defparam user_instance_name.INIT_1A = 256_bit_hex_value;

defparam user_instance_name.INIT_1B = 256_bit_hex_value;

defparam user_instance_name.INIT_1C = 256_bit_hex_value;

defparam user_instance_name.INIT_1D = 256_bit_hex_value;

defparam user_instance_name.INIT_1E = 256_bit_hex_value;

defparam user_instance_name.INIT_1F = 256_bit_hex_value;

defparam user_instance_name.INIT_20 = 256_bit_hex_value;

defparam user_instance_name.INIT_21 = 256_bit_hex_value;

defparam user_instance_name.INIT_22 = 256_bit_hex_value;

defparam user_instance_name.INIT_23 = 256_bit_hex_value;

defparam user_instance_name.INIT_24 = 256_bit_hex_value;

defparam user_instance_name.INIT_25 = 256_bit_hex_value;

defparam user_instance_name.INIT_26 = 256_bit_hex_value;

defparam user_instance_name.INIT_27 = 256_bit_hex_value;

defparam user_instance_name.INIT_28 = 256_bit_hex_value;

defparam user_instance_name.INIT_29 = 256_bit_hex_value;

defparam user_instance_name.INIT_2A = 256_bit_hex_value;

defparam user_instance_name.INIT_2B = 256_bit_hex_value;

defparam user_instance_name.INIT_2C = 256_bit_hex_value;

defparam user_instance_name.INIT_2D = 256_bit_hex_value;

defparam user_instance_name.INIT_2E = 256_bit_hex_value;

defparam user_instance_name.INIT_2F = 256_bit_hex_value;

defparam user_instance_name.INIT_30 = 256_bit_hex_value;

defparam user_instance_name.INIT_31 = 256_bit_hex_value;

defparam user_instance_name.INIT_32 = 256_bit_hex_value;

defparam user_instance_name.INIT_33 = 256_bit_hex_value;

defparam user_instance_name.INIT_34 = 256_bit_hex_value;

defparam user_instance_name.INIT_35 = 256_bit_hex_value;

defparam user_instance_name.INIT_36 = 256_bit_hex_value;

defparam user_instance_name.INIT_37 = 256_bit_hex_value;

defparam user_instance_name.INIT_38 = 256_bit_hex_value;

defparam user_instance_name.INIT_39 = 256_bit_hex_value;

defparam user_instance_name.INIT_3A = 256_bit_hex_value;

defparam user_instance_name.INIT_3B = 256_bit_hex_value;

defparam user_instance_name.INIT_3C = 256_bit_hex_value;

defparam user_instance_name.INIT_3D = 256_bit_hex_value;

defparam user_instance_name.INIT_3E = 256_bit_hex_value;

defparam user_instance_name.INIT_3F = 256_bit_hex_value;

    defparam user_instance_name.INITP_00 = 256_bit_hex_value;

    defparam user_instance_name.INITP_01 = 256_bit_hex_value;

    defparam user_instance_name.INITP_02 = 256_bit_hex_value;

    defparam user_instance_name.INITP_03 = 256_bit_hex_value;

    defparam user_instance_name.INITP_04 = 256_bit_hex_value;

    defparam user_instance_name.INITP_05 = 256_bit_hex_value;

    defparam user_instance_name.INITP_06 = 256_bit_hex_value;

    defparam user_instance_name.INITP_07 = 256_bit_hex_value;

    defparam user_instance_name.SRVAL = bit_value;

defparam user_instance_name.WRITE_MODE = write_mode;

Commonly Used Constraints

INIT

INIT_xx

SRVAL

WRITE_MODE

HU_SET

INITP_xx

SRVAL

WRITE_MODE

Component	Data Cells		Parity Cells		Address Bus	Data Bus	Parity Bus
	Depth	Width	Depth	Width
RAMB16_S1	16384	1	-	-	(13:0)	(0:0)	-
RAMB16_S2	8192	2	-	-	(12:0)	(1:0)	-
RAMB16_S4	4096	4	-	-	(11:0)	(3:0)	-
RAMB16_S9	2048	8	2048	1	(10:0)	(7:0)	(0:0)
RAMB16_S18	1024	16	1024	2	(9:0)	(15:0)	(1:0)
RAMB16_S36	512	32	512	4	(8:0)	(31:0)	(3:0)

Inputs								Outputs
GSR	EN	SSR	WE	CLK	ADDR	DI	DIP	DO	DOP	RAM Contents
										Data RAM	Parity RAM
1	X	X	X	X	X	X	X	INIT	INIT	No Chg	No Chg
0	0	X	X	X	X	X	X	No Chg	No Chg	No Chg	No Chg
0	1	1	0		X	X	X	SRVAL	SRVAL	No Chg	No Chg
0	1	1	1		addr	data	pdata	SRVAL	SRVAL	RAM(addr) =>data	RAM(addr) =>pdata
0	1	0	0		addr	X	X	RAM(addr)	RAM(addr)	No Chg	No Chg
0	1	0	1		addr	data	pdata	No Chga RAM (addr)b datac	No Chga RAM(addr)b pdatac	RAM(addr) =>data	RAM(addr) =>pdata
GSR=Global Set Reset signal INIT=Value specified by the INIT attribute for data memory. Default is all zeros. SRVAL=Value after assertion of SSR as specified by the SRVAL attribute. addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data pdata=RAM parity data aWRITE_MODE=NO_CHANGE bWRITE_MODE=READ_FIRST cWRITE_MODE=WRITE_FIRST