RAMB16_Sm

RAMB16_Sm_Sn

16384-Bit Data Memory and 2048-Bit Parity Memory, Dual-Port Synchronous Block RAM with Port Width (m or n) Configured to 1, 2, 4, 9, 18, or 36 Bits

Spartan-II,

Spartan-IIE

Spartan-3

Virtex,

Virtex-E

Virtex-II,

Virtex-II Pro,
Virtex-II Pro X

XC9500/XV/XL

CoolRunner

XPLA3

CoolRunner-II

N/A

Primitive

N/A

Primitive

N/A

N/A

N/A

RAMB16_S1_S1 through RAMB16_S1_S36 Representations

RAMB16_S2_S2 through RAMB16_S4_S36 Representations

RAMB16_S9_S9 through RAMB16_S36_S36 Representations

The RAMB16_Sm_Sn components listed in the following table are dual-ported dedicated random access memory blocks with synchronous write capability. Each block RAM port has 16384 bits of data memory. Ports configured as 9, 18, or 36-bits wide have an additional 2048 bits of parity memory. Each port is independent of the other while accessing the same set of 16384 data memory cells. Each port is independently configured to a specific data width. The possible port and cell configurations are listed in the following table.

Port A

Port B

Component

Data Cellsa

Parity Cellsa

Address Bus

Data Bus

Parity Bus

Data Cellsa

Parity Cellsa

Address Bus

Data Bus

Parity Bus

RAMB16_S1_S1

16384 x 1

-

(13:0)

(0:0)

-

16384 x 1

-

(13:0)

(0:0)

-

RAMB16_S1_S2

16384 x 1

-

(13:0)

(0:0)

-

8192 x 2

-

(12:0)

(1:0)

-

RAMB16_S1_S4

16384 x 1

-

(13:0)

(0:0)

-

4096 x 4

-

(11:0)

(3:0)

-

RAMB16_S1_S9

16384 x 1

-

(13:0)

(0:0)

-

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S1_S18

16384 x 1

-

(13:0)

(0:0)

-

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S1_S36

16384 x 1

-

(13:0)

(0:0)

-

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S2_S2

8192 x 2

-

(12:0)

(1:0)

-

8192 x 2

-

(12:0)

(1:0)

-

RAMB16_S2_S4

8192 x 2

-

(12:0)

(1:0)

-

4096 x 4

-

(11:0)

(3:0)

-

RAMB16_S2_S9

8192 x 2

-

(12:0)

(1:0)

-

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S2_S18

8192 x 2

-

(12:0)

(1:0)

-

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S2_S36

8192 x 2

-

(12:0)

(1:0)

-

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S4_S4

4096 x 4

-

(11:0)

(3:0)

-

4096 x 4

-

(11:0)

(3:0)

-

RAMB16_S4_S9

4096 x 4

-

(11:0)

(3:0)

-

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S4_S18

4096 x 4

-

(11:0)

(3:0)

-

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S4_S36

4096 x 4

-

(11:0)

(3:0)

-

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S9_S9

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

RAMB16_S9_S18

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S9_S36

2048 x 8

2048 x 1

(10:0)

(7:0)

(0:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S18_S18

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

RAMB16_S18_S36

1024 x 16

1024 x 2

(9:0)

(15:0)

(1:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

RAMB16_S36_S36

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

512 x 32

512 x 4

(8:0)

(31:0)

(3:0)

aDepth x Width

Each port is fully synchronous with independent clock pins. All port A input pins have setup time referenced to the CLKA pin and its data output bus DOA has a clock-to-out time referenced to the CLKA. All port B input pins have setup time referenced to the CLKB pin and its data output bus DOB has a clock-to-out time referenced to the CLKB.

The enable ENA pin controls read, write, and reset for port A. When ENA is Low, no data is written and the outputs (DOA and DOPA) retain the last state. When ENA is High and reset (SSRA) is High, DOA and DOPA are set to SRVAL_A during the Low-to-High clock (CLKA) transition; if write enable (WEA) is High, the memory contents reflect the data at DIA and DIPA. When ENA is High and WEA is Low, the data stored in the RAM address (ADDRA) is read during the Low-to-High clock transition. By default, WRITE_MODE_A=WRITE_FIRST, when ENA and WEA are High, the data on the data inputs (DIA and DIPA) is loaded into the word selected by the write address (ADDRA) during the Low-to-High clock transition and the data outputs (DOA and DOPA) reflect the selected (addressed) word.

The enable ENB pin controls read, write, and reset for port B. When ENB is Low, no data is written and the outputs (DOB and DOPB) retain the last state. When ENB is High and reset (SSRB) is High, DOB and DOPB are set to SRVAL_B during the Low-to-High clock (CLKB) transition; if write enable (WEB) is High, the memory contents reflect the data at DIB and DIPB. When ENB is High and WEB is Low, the data stored in the RAM address (ADDRB) is read during the Low-to-High clock transition. By default, WRITE_MODE_B=WRITE_FIRST, when ENB and WEB are High, the data on the data inputs (DIB and PB) are loaded into the word selected by the write address (ADDRB) during the Low-to-High clock transition and the data outputs (DOB and DOPB) reflect the selected (addressed) word.

The above descriptions assume active High control pins (ENA, WEA, SSRA, CLKA, ENB, WEB, SSRB, and CLKB). However, the active level can be changed by placing an inverter on the port. Any inverter placed on a RAMB16 port is absorbed into the block and does not use a CLB resource.

Port A Truth Table

Inputs

Outputs

GSR

ENA

SSRA

WEA

CLKA

ADDRA

DIA

DIPA

DOA

DOPA

RAM Contents

Data RAM

Parity RAM

1

X

X

X

X

X

X

X

INIT_A

INIT_A

No Chg

No Chg

0

0

X

X

X

X

X

X

No Chg

No Chg

No Chg

No Chg

0

1

1

0

X

X

X

SRVAL_A

SRVAL_A

No Chg

No Chg

0

1

1

1

addr

data

pdata

SRVAL_A

SRVAL_A

RAM(addr) =>data

RAM(addr) =>pdata

0

1

0

0

addr

X

X

RAM(addr)

RAM(addr)

No Chg

No Chg

0

1

0

1

addr

data

pdata

No Chg1
RAM (addr)2
data3

No Chg1
RAM(addr)2
pdata3

RAM(addr) =>data

RAM(addr) =>pdata

GSR=Global Set Reset

INIT_A=Value specified by the INIT_A attribute for output register. Default is all zeros.
SRVAL_A=register value

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data

pdata=RAM parity data

1WRITE_MODE_A=NO_CHANGE

2WRITE_MODE_A=READ_FIRST

3WRITE_MODE_A=WRITE_FIRST

Port B Truth Table

Inputs

Outputs

GSR

ENB

SSRB

WEB

CLKB

ADDRB

DIB

DIPB

DOB

DOPB

RAM Contents

Data RAM

Parity RAM

1

X

X

X

X

X

X

X

INIT_B

INIT_B

No Chg

No Chg

0

0

X

X

X

X

X

X

No Chg

No Chg

No Chg

No Chg

0

1

1

0

X

X

X

SRVAL_B

SRVAL_B

No Chg

No Chg

0

1

1

1

addr

data

pdata

SRVAL_B

SRVAL_B

RAM(addr) =>data

RAM(addr) =>pdata

0

1

0

0

addr

X

X

RAM(addr)

RAM(addr)

No Chg

No Chg

0

1

0

1

addr

data

pdata

No Chg1
RAM (addr)2
data3

No Chg1
RAM(addr)2
pdata3

RAM(addr) =>data

RAM(addr) =>pdata

GSR=Global Set Reset

INIT_B=Value specified by the INIT_B attribute for output registers. Default is all zeros.
SRVAL_B=register value

addr=RAM address
RAM(addr)=RAM contents at address ADDR
data=RAM input data

pdata=RAM parity data

1WRITE_MODE_B=NO_CHANGE

2WRITE_MODE_B=READ_FIRST

3WRITE_MODE_B=WRITE_FIRST

Address Mapping

Each port accesses the same set of 18432 memory cells using an addressing scheme that is dependent on the width of the port. For all port widths, 16384 memory cells are available for data as shown in the “Port Address Mapping for Data” table . For 9-, 18-, and 36-bit wide ports, 2408 parity memory cells are also available as shown in “Port Address Mapping for Parity” table. The physical RAM location that is addressed for a particular width is determined from the following formula.

   Start=((ADDR port+1)*(Widthport)) -1

   End=(ADDRport)*(Widthport)

The following tables shows address mapping for each port width.

Port Address Mapping for Data

DataWidth

Port Data Addresses

1

16384

<--

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

2

8192

<--

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

4

4096

<--

07

06

05

04

03

02

01

00

8

2048

<--

03

02

01

00

16

1024

<--

01

00

32

512

<--

00

Port Address Mapping for Parity

Parity Width

Port Parity Addresses

1

2048

<-----

03

02

01

00

2

1024

<-----

01

00

4

512

<-----

00

Initializing Memory Contents of a Dual-Port RAMB16

You can use the INIT_xx attributes to specify an initialization value for the memory contents of a RAMB16 during device configuration. The initialization of each RAMB16_Sm_Sn is set by 64 initialization attributes (INIT_00 through INIT_3F) of 64 hex values for a total of 16384 bits.

You can use the INITP_xx attributes to specify an initial value for the parity memory during device configuration or assertion. The initialization of the parity memory for ports configured for 9, 18, or 36 bits is set by 8 initialization attributes (INITP_00 through INITP_07) of 64 hex values for a total of 2048 bits.

If any INIT_xx or INITP_xx attribute is not specified, it is configured as zeros. Partial strings are padded with zeros to the left.

See the Constraints Guide for more information on these attributes.

Initializing the Output Register of a Dual-Port RAMB16

In Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X, each bit in an output register can be initialized at power on (when GSR is high) to either a 0 or 1. In addition, the initial state specified for power on can be different than the state that results from assertion of a set/reset. Four properties control initialization of the output register for a dual-port RAMB16: INIT_A, INIT_B, SRVAL_A, and SRVAL_B. The INIT_A attribute specifies the output register value at power on for port A and the INIT_B attribute specifies the value for port B. You can use the SRVAL_A attribute to define the state resulting from assertion of the SSR (set/reset) input on port A. You can use the SRVAL_B attribute to define the state resulting from assertion of the SSR input on port B.

The INIT_A, INIT_B, SRVAL_A, and SRVAL_B attributes specify the initialization value as a hexadecimal string. The value is dependent upon the port width. For example, for a RAMB16_S1_S4 with port A width equal to 1 and port B width equal to 4, the port A output register contains 1 bit and the port B output register contains 4 bits. Therefore, the INIT_A or SRVAL_A value can only be specified as a 1 or 0. For port B, the output register contains 4 bits. In this case, you can use INIT_B or SRVAL_B to specify a hexadecimal value from 0 through F to initialize the 4 bits of the output register.

For those ports that include parity bits, the parity portion of the output register is specified in the high order bit position of the INIT_A, INIT_B, SRVAL_A, or SRVAL_B value.

The INIT and SRVAL attributes default to zero if they are not set by the user.

See the Constraints Guide for more information on these attributes.

Write Mode Selection

The WRITE_MODE_A attribute controls the memory and output contents of port A for a dual-port RAMB16. The WRITE_MODE_B attribute does the same for port B. By default, both WRITE_MODE_A and WRITE_MODE_B are set to WRITE_FIRST. This means that input is read, written to memory, and then passed to output. You can set the write mode for port A and/or port B to READ_FIRST to read the memory contents, pass the memory contents to the outputs, and then write the input to memory. Or, you can set the write mode to NO_CHANGE to have the input written to memory without changing the output. The “Port A and Port B Conflict Resolution” section describes how read/write conflicts are resolved when both port A and port B are attempting to read/write to the same memory cells.

Port A and Port B Conflict Resolution

Spartan-3, Virtex-II, Virtex-II Pro, and Virtex-II Pro X block SelectRAM is True Dual-Port RAM that allows both ports to simultaneously access the same memory cell. When one port writes to a given memory cell, the other port must not address that memory cell (for a write or a read) within the clock-to-clock setup window. For a list of specifics of conflict resolution for port and memory cell write operations that have either a clock common to both ports or synchronous clocks on each port, see Virtex-II Handbook, Chapter 2, Design Considerations, Using BlockSelectRAM Memory, Conflict Resolution.

The following tables summarize the collision detection behavior of the dual-port RAMB16 based on the WRITE_MODE_A and WRITE_MODE_B settings.

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=NO_CHANGE

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data RAM

Parity Ram

0

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg

No Chg

1

0

DIA

DIB

DIPA

DIPB

No Chg

X

No Chg

X

DIA

DIPA

0

1

DIA

DIB

DIPA

DIPB

X

No Chg

X

No Chg

DIB

DIPB

1

1

DIA

DIB

DIPA

DIPB

No Chg

No Chg

No Chg

No Chg

X

X

WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=READ_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data RAM

Parity Ram

0

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg

No Chg

1

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIPA

0

1

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIB

DIPB

1

1

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

X

X

WRITE_MODE_A= WRITE_FIRST and WRITE_MODE_B=WRITE_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data RAM

Parity Ram

0

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg

No Chg

1

0

DIA

DIB

DIPA

DIPB

DIA

X

DIPA

X

DIA

DIPA

0

1

DIA

DIB

DIPA

DIPB

X

DIB

X

DIPB

DIB

DIPB

1

1

DIA

DIB

DIPA

DIPB

X

X

X

X

X

X

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=READ_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data RAM

Parity Ram

0

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg

No Chg

1

0

DIA

DIB

DIPA

DIPB

No Chg

X

No Chg

X

DIA

DIPA

0

1

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIB

DIPB

1

1

DIA

DIB

DIPA

DIPB

No Chg

X

No Chg

X

DIB

DIPB

WRITE_MODE_A=NO_CHANGE and WRITE_MODE_B=WRITE_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data RAM

Parity Ram

0

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg

No Chg

1

0

DIA

DIB

DIPA

DIPB

No Chg

X

No Chg

X

DIA

DIPA

0

1

DIA

DIB

DIPA

DIPB

X

DIB

X

DIPB

DIB

DIPB

1

1

DIA

DIB

DIPA

DIPB

No Chg

X

No Chg

X

X

X

WRITE_MODE_A=READ_FIRST and WRITE_MODE_B=WRITE_FIRST

WEA

WEB

CLKA

CLKB

DIA

DIB

DIPA

DIPB

DOA

DOB

DOPA

DOPB

Data RAM

Parity Ram

0

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

No Chg

No Chg

1

0

DIA

DIB

DIPA

DIPB

RAM

RAM

RAM

RAM

DIA

DIPA

0

1

DIA

DIB

DIPA

DIPB

X

DIB

X

DIPB

DIB

DIPB

1

1

DIA

DIB

DIPA

DIPB

X

DIB

X

DIPB

DIA

DIPA

Usage

For HDL, these design elements can be inferred or instantiated. The instantiation code is shown below. For information on how to infer RAM, see the XST User Guide.

VHDL Instantiation Template for RAMB16_S1_S1, RAMB16_S1_S2, RAMB16_S1_S4, RAMB16_S2_S2, RAMB16_S2_S4, and RAMB16_S4_S4

-- Component Declaration for RAMB16_S1_{S1 | S2 | S4}, RAMB16_S2_{S2 | S4}, and

-- RAMB16_S4_S4 should be placed after architecture statement but before begin keyword

-- For the following component declaration, enter RAMB16_S1_{S1 | S2 | S4},

-- RAMB16_S2_{S2 | S4}, or RAMB16_S4_S4

component RAMB16_Sm_Sn

-- synthesis translate_off

generic (

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INIT_A : bit_vector := X"0";

       INIT_B : bit_vector := X"0";

       INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       SRVAL_A : bit_vector := X"0";

       SRVAL_B : bit_vector := X"0";

       WRITE_MODE_A : string := "WRITE_FIRST";

       WRITE_MODE_B : string := "WRITE_FIRST";

);

-- synthesis translate_on

   port (DOA : out STD_LOGIC_VECTOR (n downto 0);

         DOB : out STD_LOGIC_VECTOR (n downto 0);

         ADDRA : in STD_LOGIC_VECTOR (n downto 0);

         ADDRB : in STD_LOGIC_VECTOR (n downto 0);

         CLKA : in STD_ULOGIC;

         CLKB : in STD_ULOGIC;

         DIA : in STD_LOGIC_VECTOR (n downto 0);

         DIB : in STD_LOGIC_VECTOR (n downto 0);

         ENA : in STD_ULOGIC;

         ENB : in STD_ULOGIC;

         SSRA : in STD_ULOGIC;

         SSRB : in STD_ULOGIC;

         WEA : in STD_ULOGIC;

         WEB : in STD_ULOGIC);

end component;

-- Component Attribute Specification for design element

-- should be placed after architecture declaration

-- but before the begin keyword

-- Put attributes, if necessary

-- Component Instantiation for design element

-- Should be placed in architecture after the begin keyword

RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn

-- synthesis translate_off

generic map (

INIT_00 => vector_value,

INIT_01 => vector_value,

INIT_02 => vector_value,

INIT_03 => vector_value,

INIT_04 => vector_value,

INIT_05 => vector_value,

INIT_06 => vector_value,

INIT_07 => vector_value,

INIT_08 => vector_value,

INIT_09 => vector_value,

INIT_0A => vector_value,

INIT_0B => vector_value,

INIT_0C => vector_value,

INIT_0D => vector_value,

INIT_0E => vector_value,

INIT_0F => vector_value,

INIT_10 => vector_value,

INIT_11 => vector_value,

INIT_12 => vector_value,

INIT_13 => vector_value,

INIT_14 => vector_value,

INIT_15 => vector_value,

INIT_16 => vector_value,

INIT_17 => vector_value,

INIT_18 => vector_value,

INIT_19 => vector_value,

INIT_1A => vector_value,

INIT_1B => vector_value,

INIT_1C => vector_value,

INIT_1D => vector_value,

INIT_1E => vector_value,

INIT_1F => vector_value,

INIT_20 => vector_value,

INIT_21 => vector_value,

INIT_22 => vector_value,

INIT_23 => vector_value,

INIT_24 => vector_value,

INIT_25 => vector_value,

INIT_26 => vector_value,

INIT_27 => vector_value,

INIT_28 => vector_value,

INIT_29 => vector_value,

INIT_2A => vector_value,

INIT_2B => vector_value,

INIT_2C => vector_value,

INIT_2D => vector_value,

INIT_2E => vector_value,

INIT_2F => vector_value,

INIT_30 => vector_value,

INIT_31 => vector_value,

INIT_32 => vector_value,

INIT_33 => vector_value,

INIT_34 => vector_value,

INIT_35 => vector_value,

INIT_36 => vector_value,

INIT_37 => vector_value,

INIT_38 => vector_value,

INIT_39 => vector_value,

INIT_3A => vector_value,

INIT_3B => vector_value,

INIT_3C => vector_value,

INIT_3D => vector_value,

INIT_3E => vector_value,

INIT_3F => vector_value,

       INIT_A => bit_value,

       INIT_B => bit_value,

       INITP_00 => vector_value,

       INITP_01 => vector_value,

       INITP_02 => vector_value,

       INITP_03 => vector_value,

       INITP_04 => vector_value,

       INITP_05 => vector_value,

       INITP_06 => vector_value,

       INITP_07 => vector_value,

       SRVAL_A => bit_value,

       SRVAL_B => bit_value,

       WRITE_MODE_A => string_value,

       WRITE_MODE_B => string_value)

   -- synopsys translate_on

   port map (DOA => user_DOA,

             DOB => user_DOB,

             ADDRA => user_ADDRA,

             ADDRB => user_ADDRB,

             CLKA => user_CLKA,

             CLKB => user_CLKB,

             DIA => user_DIA,

             DIB => user_DIB,

             ENA => user_ENA,

             ENB => user_ENB,

             SSRA => user_SSRA,

             SSRB => user_SSRB,

             WEA => user_WEA,

             WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S1_S1, RAMB16_S1_S2, RAMB16_S1_S4, RAMB16_S2_S2, RAMB16_S2_S4, and RAMB16_S4_S4

RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA),

                                 .DOB (user_DOB),

                                 .ADDRA (user_ADDRA),

                                 .ADDRB (user_ADDRB),

                                 .CLKA (user_CLKA),

                                 .CLKB (user_CLKB),

                                 .DIA (user_DIA),

                                 .DIB (user_DIB),

                                 .ENA (user_ENA),

                                 .ENB (user_ENB),

                                 .SSRA (user_SSRA),

                                 .SSRB (user_SSRB),

                                 .WEA (user_WEA),

                                  .WEB (user_WEB));

defparam user_instance_name.INIT_00 = 256_bit_hex_value;

defparam user_instance_name.INIT_01 = 256_bit_hex_value;

defparam user_instance_name.INIT_02 = 256_bit_hex_value;

defparam user_instance_name.INIT_03 = 256_bit_hex_value;

defparam user_instance_name.INIT_04 = 256_bit_hex_value;

defparam user_instance_name.INIT_05 = 256_bit_hex_value;

defparam user_instance_name.INIT_06 = 256_bit_hex_value;

defparam user_instance_name.INIT_07 = 256_bit_hex_value;

defparam user_instance_name.INIT_08 = 256_bit_hex_value;

defparam user_instance_name.INIT_09 = 256_bit_hex_value;

defparam user_instance_name.INIT_0A = 256_bit_hex_value;

defparam user_instance_name.INIT_0B = 256_bit_hex_value;

defparam user_instance_name.INIT_0C = 256_bit_hex_value;

defparam user_instance_name.INIT_0D = 256_bit_hex_value;

defparam user_instance_name.INIT_0E = 256_bit_hex_value;

defparam user_instance_name.INIT_0F = 256_bit_hex_value;

defparam user_instance_name.INIT_10 = 256_bit_hex_value;

defparam user_instance_name.INIT_11 = 256_bit_hex_value;

defparam user_instance_name.INIT_12 = 256_bit_hex_value;

defparam user_instance_name.INIT_13 = 256_bit_hex_value;

defparam user_instance_name.INIT_14 = 256_bit_hex_value;

defparam user_instance_name.INIT_15 = 256_bit_hex_value;

defparam user_instance_name.INIT_16 = 256_bit_hex_value;

defparam user_instance_name.INIT_17 = 256_bit_hex_value;

defparam user_instance_name.INIT_18 = 256_bit_hex_value;

defparam user_instance_name.INIT_19 = 256_bit_hex_value;

defparam user_instance_name.INIT_1A = 256_bit_hex_value;

defparam user_instance_name.INIT_1B = 256_bit_hex_value;

defparam user_instance_name.INIT_1C = 256_bit_hex_value;

defparam user_instance_name.INIT_1D = 256_bit_hex_value;

defparam user_instance_name.INIT_1E = 256_bit_hex_value;

defparam user_instance_name.INIT_1F = 256_bit_hex_value;

defparam user_instance_name.INIT_20 = 256_bit_hex_value;

defparam user_instance_name.INIT_21 = 256_bit_hex_value;

defparam user_instance_name.INIT_22 = 256_bit_hex_value;

defparam user_instance_name.INIT_23 = 256_bit_hex_value;

defparam user_instance_name.INIT_24 = 256_bit_hex_value;

defparam user_instance_name.INIT_25 = 256_bit_hex_value;

defparam user_instance_name.INIT_26 = 256_bit_hex_value;

defparam user_instance_name.INIT_27 = 256_bit_hex_value;

defparam user_instance_name.INIT_28 = 256_bit_hex_value;

defparam user_instance_name.INIT_29 = 256_bit_hex_value;

defparam user_instance_name.INIT_2A = 256_bit_hex_value;

defparam user_instance_name.INIT_2B = 256_bit_hex_value;

defparam user_instance_name.INIT_2C = 256_bit_hex_value;

defparam user_instance_name.INIT_2D = 256_bit_hex_value;

defparam user_instance_name.INIT_2E = 256_bit_hex_value;

defparam user_instance_name.INIT_2F = 256_bit_hex_value;

defparam user_instance_name.INIT_30 = 256_bit_hex_value;

defparam user_instance_name.INIT_31 = 256_bit_hex_value;

defparam user_instance_name.INIT_32 = 256_bit_hex_value;

defparam user_instance_name.INIT_33 = 256_bit_hex_value;

defparam user_instance_name.INIT_34 = 256_bit_hex_value;

defparam user_instance_name.INIT_35 = 256_bit_hex_value;

defparam user_instance_name.INIT_36 = 256_bit_hex_value;

defparam user_instance_name.INIT_37 = 256_bit_hex_value;

defparam user_instance_name.INIT_38 = 256_bit_hex_value;

defparam user_instance_name.INIT_39 = 256_bit_hex_value;

defparam user_instance_name.INIT_3A = 256_bit_hex_value;

defparam user_instance_name.INIT_3B = 256_bit_hex_value;

defparam user_instance_name.INIT_3C = 256_bit_hex_value;

defparam user_instance_name.INIT_3D = 256_bit_hex_value;

defparam user_instance_name.INIT_3E = 256_bit_hex_value;

defparam user_instance_name.INIT_3F = 256_bit_hex_value;

    defparam user_instance_name.INIT_A = bit_value;

    defparam user_instance_name.INIT_B = bit_value;

    defparam user_instance_name.INITP_00 = 256_bit_hex_value;

    defparam user_instance_name.INITP_01 = 256_bit_hex_value;

    defparam user_instance_name.INITP_02 = 256_bit_hex_value;

    defparam user_instance_name.INITP_03 = 256_bit_hex_value;

    defparam user_instance_name.INITP_04 = 256_bit_hex_value;

    defparam user_instance_name.INITP_05 = 256_bit_hex_value;

    defparam user_instance_name.INITP_06 = 256_bit_hex_value;

    defparam user_instance_name.INITP_07 = 256_bit_hex_value;

    defparam user_instance_name.SRVAL_A = bit_value;

    defparam user_instance_name.SRVAL_B = bit_value;

    defparam user_instance_name.WRITE_MODE_A = string_value;

    defparam user_instance_name.WRITE_MODE_B = string_value;

VHDL Instantiation Template for RAMB16_S1_S9, RAMB16_S1_S18, RAMB16_S1_S36, RAMB16_S2_S9, RAMB16_S2_S18, RAMB16_S2_S36, RAMB16_S4_S9, RAMB16_S4_S18, and RAMB16_S4_S36

-- Component Declaration for these design elements

-- should be placed after architecture statement but before begin keyword

-- For the following component declaration, enter RAMB16_S1_{S9 | S18 | S36},

-- RAMB16_S2_{S9 | S18 | S36}, or RAMB16_S4_{S9 | S18 | S36}

component RAMB16_Sm_Sn

-- synthesis translate_off

generic (

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INIT_A : bit_vector := X"0";

       INIT_B : bit_vector := X"0";

       INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       SRVAL_A : bit_vector := X"0";

       SRVAL_B : bit_vector := X"0";

       WRITE_MODE_A : string := "WRITE_FIRST";

       WRITE_MODE_B : string := "WRITE_FIRST";

);

   -- synthesis translate_on

   port (DOA : out STD_LOGIC_VECTOR (n downto 0);

         DOB : out STD_LOGIC_VECTOR (n downto 0);

         DOPB : out STD_LOGIC_VECTOR (n downto 0);

         ADDRA : in STD_LOGIC_VECTOR (n downto 0);

         ADDRB : in STD_LOGIC_VECTOR (n downto 0);

         CLKA : in STD_ULOGIC;

         CLKB : in STD_ULOGIC;

         DIA : in STD_LOGIC_VECTOR (n downto 0);

         DIB : in STD_LOGIC_VECTOR (n downto 0);

         DIPB : in STD_LOGIC_VECTOR (n downto 0);

         ENA : in STD_ULOGIC;

         ENB : in STD_ULOGIC;

         SSRA : in STD_ULOGIC;

         SSRB : in STD_ULOGIC;

         WEA : in STD_ULOGIC;

         WEB : in STD_ULOGIC);

end component;

-- Component Attribute Specification for design element

-- should be placed after architecture declaration

-- but before the begin keyword

-- Put attributes, if necessary

-- Component Instantiation for design element

-- Should be placed in architecture after the begin keyword

RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn

-- synthesis translate_off

generic map (

       INIT_00 => vector_value,

INIT_01 => vector_value,

INIT_02 => vector_value,

INIT_03 => vector_value,

INIT_04 => vector_value,

INIT_05 => vector_value,

INIT_06 => vector_value,

INIT_07 => vector_value,

INIT_08 => vector_value,

INIT_09 => vector_value,

INIT_0A => vector_value,

INIT_0B => vector_value,

INIT_0C => vector_value,

INIT_0D => vector_value,

INIT_0E => vector_value,

INIT_0F => vector_value,

INIT_10 => vector_value,

INIT_11 => vector_value,

INIT_12 => vector_value,

INIT_13 => vector_value,

INIT_14 => vector_value,

INIT_15 => vector_value,

INIT_16 => vector_value,

INIT_17 => vector_value,

INIT_18 => vector_value,

INIT_19 => vector_value,

INIT_1A => vector_value,

INIT_1B => vector_value,

INIT_1C => vector_value,

INIT_1D => vector_value,

INIT_1E => vector_value,

INIT_1F => vector_value,

INIT_20 => vector_value,

INIT_21 => vector_value,

INIT_22 => vector_value,

INIT_23 => vector_value,

INIT_24 => vector_value,

INIT_25 => vector_value,

INIT_26 => vector_value,

INIT_27 => vector_value,

INIT_28 => vector_value,

INIT_29 => vector_value,

INIT_2A => vector_value,

INIT_2B => vector_value,

INIT_2C => vector_value,

INIT_2D => vector_value,

INIT_2E => vector_value,

INIT_2F => vector_value,

INIT_30 => vector_value,

INIT_31 => vector_value,

INIT_32 => vector_value,

INIT_33 => vector_value,

INIT_34 => vector_value,

INIT_35 => vector_value,

INIT_36 => vector_value,

INIT_37 => vector_value,

INIT_38 => vector_value,

INIT_39 => vector_value,

INIT_3A => vector_value,

INIT_3B => vector_value,

INIT_3C => vector_value,

INIT_3D => vector_value,

INIT_3E => vector_value,

INIT_3F => vector_value,

       INIT_A => bit_value,

       INIT_B => bit_value,

       INITP_00 => vector_value,

       INITP_01 => vector_value,

       INITP_02 => vector_value,

       INITP_03 => vector_value,

       INITP_04 => vector_value,

       INITP_05 => vector_value,

       INITP_06 => vector_value,

       INITP_07 => vector_value,

       SRVAL_A => bit_value,

       SRVAL_B => bit_value,

       WRITE_MODE_A => string_value,

       WRITE_MODE_B => string_value)

   -- synopsys translate_on

   port map (DOA => user_DOA,

             DOB => user_DOB,

             DOPB => user_DOPB,

             ADDRA => user_ADDRA,

             ADDRB => user_ADDRB,

             CLKA => user_CLKA,

             CLKB => user_CLKB,

             DIA => user_DIA,

             DIB => user_DIB,

             DIPB => user_DIPB,

             ENA => user_ENA,

             ENB => user_ENB,

             SSRA => user_SSRA,

             SSRB => user_SSRB,

             WEA => user_WEA,

             WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S1_S9, RAMB16_S1_S18, RAMB16_S1_S36, RAMB16_S2_S9, RAMB16_S2_S18, RAMB16_S2_S36, RAMB16_S4_S9, RAMB16_S4_S18, and RAMB16_S4_S36

RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA),

                                 .DOB (user_DOB),

                                 .DOPB (user_DOPB),

                                 .ADDRA (user_ADDRA),

                                 .ADDRB (user_ADDRB),

                                 .CLKA (user_CLKA),

                                 .CLKB (user_CLKB),

                                 .DIA (user_DIA),

                                 .DIB (user_DIB),

                                 .DIPB (user_DIB),

                                 .ENA (user_ENA),

                                 .ENB (user_ENB),

                                 .SSRA (user_SSRA),

                                 .SSRB (user_SSRB),

                                 .WEA (user_WEA),

                                 .WEB (user_WEB));

    defparam user_instance_name.INIT_00 = 256_bit_hex_value;

defparam user_instance_name.INIT_01 = 256_bit_hex_value;

defparam user_instance_name.INIT_02 = 256_bit_hex_value;

defparam user_instance_name.INIT_03 = 256_bit_hex_value;

defparam user_instance_name.INIT_04 = 256_bit_hex_value;

defparam user_instance_name.INIT_05 = 256_bit_hex_value;

defparam user_instance_name.INIT_06 = 256_bit_hex_value;

defparam user_instance_name.INIT_07 = 256_bit_hex_value;

defparam user_instance_name.INIT_08 = 256_bit_hex_value;

defparam user_instance_name.INIT_09 = 256_bit_hex_value;

defparam user_instance_name.INIT_0A = 256_bit_hex_value;

defparam user_instance_name.INIT_0B = 256_bit_hex_value;

defparam user_instance_name.INIT_0C = 256_bit_hex_value;

defparam user_instance_name.INIT_0D = 256_bit_hex_value;

defparam user_instance_name.INIT_0E = 256_bit_hex_value;

defparam user_instance_name.INIT_0F = 256_bit_hex_value;

defparam user_instance_name.INIT_10 = 256_bit_hex_value;

defparam user_instance_name.INIT_11 = 256_bit_hex_value;

defparam user_instance_name.INIT_12 = 256_bit_hex_value;

defparam user_instance_name.INIT_13 = 256_bit_hex_value;

defparam user_instance_name.INIT_14 = 256_bit_hex_value;

defparam user_instance_name.INIT_15 = 256_bit_hex_value;

defparam user_instance_name.INIT_16 = 256_bit_hex_value;

defparam user_instance_name.INIT_17 = 256_bit_hex_value;

defparam user_instance_name.INIT_18 = 256_bit_hex_value;

defparam user_instance_name.INIT_19 = 256_bit_hex_value;

defparam user_instance_name.INIT_1A = 256_bit_hex_value;

defparam user_instance_name.INIT_1B = 256_bit_hex_value;

defparam user_instance_name.INIT_1C = 256_bit_hex_value;

defparam user_instance_name.INIT_1D = 256_bit_hex_value;

defparam user_instance_name.INIT_1E = 256_bit_hex_value;

defparam user_instance_name.INIT_1F = 256_bit_hex_value;

defparam user_instance_name.INIT_20 = 256_bit_hex_value;

defparam user_instance_name.INIT_21 = 256_bit_hex_value;

defparam user_instance_name.INIT_22 = 256_bit_hex_value;

defparam user_instance_name.INIT_23 = 256_bit_hex_value;

defparam user_instance_name.INIT_24 = 256_bit_hex_value;

defparam user_instance_name.INIT_25 = 256_bit_hex_value;

defparam user_instance_name.INIT_26 = 256_bit_hex_value;

defparam user_instance_name.INIT_27 = 256_bit_hex_value;

defparam user_instance_name.INIT_28 = 256_bit_hex_value;

defparam user_instance_name.INIT_29 = 256_bit_hex_value;

defparam user_instance_name.INIT_2A = 256_bit_hex_value;

defparam user_instance_name.INIT_2B = 256_bit_hex_value;

defparam user_instance_name.INIT_2C = 256_bit_hex_value;

defparam user_instance_name.INIT_2D = 256_bit_hex_value;

defparam user_instance_name.INIT_2E = 256_bit_hex_value;

defparam user_instance_name.INIT_2F = 256_bit_hex_value;

defparam user_instance_name.INIT_30 = 256_bit_hex_value;

defparam user_instance_name.INIT_31 = 256_bit_hex_value;

defparam user_instance_name.INIT_32 = 256_bit_hex_value;

defparam user_instance_name.INIT_33 = 256_bit_hex_value;

defparam user_instance_name.INIT_34 = 256_bit_hex_value;

defparam user_instance_name.INIT_35 = 256_bit_hex_value;

defparam user_instance_name.INIT_36 = 256_bit_hex_value;

defparam user_instance_name.INIT_37 = 256_bit_hex_value;

defparam user_instance_name.INIT_38 = 256_bit_hex_value;

defparam user_instance_name.INIT_39 = 256_bit_hex_value;

defparam user_instance_name.INIT_3A = 256_bit_hex_value;

defparam user_instance_name.INIT_3B = 256_bit_hex_value;

defparam user_instance_name.INIT_3C = 256_bit_hex_value;

defparam user_instance_name.INIT_3D = 256_bit_hex_value;

defparam user_instance_name.INIT_3E = 256_bit_hex_value;

defparam user_instance_name.INIT_3F = 256_bit_hex_value;

    defparam user_instance_name.INIT_A = bit_value;

    defparam user_instance_name.INIT_B = bit_value;

    defparam user_instance_name.INITP_00 = 256_bit_hex_value;

    defparam user_instance_name.INITP_01 = 256_bit_hex_value;

    defparam user_instance_name.INITP_02 = 256_bit_hex_value;

    defparam user_instance_name.INITP_03 = 256_bit_hex_value;

    defparam user_instance_name.INITP_04 = 256_bit_hex_value;

    defparam user_instance_name.INITP_05 = 256_bit_hex_value;

    defparam user_instance_name.INITP_06 = 256_bit_hex_value;

    defparam user_instance_name.INITP_07 = 256_bit_hex_value;

    defparam user_instance_name.SRVAL_A = bit_value;

    defparam user_instance_name.SRVAL_B = bit_value;

    defparam user_instance_name.WRITE_MODE_A = string_value;

    defparam user_instance_name.WRITE_MODE_B = string_value;

VHDL Instantiation Template RAMB16_S9_S9, RAMB16_S9_S18, RAMB16_S9_S36, RAMB16_S18_S18, RAMB16_S18_S36, and RAMB16_S36_S36

-- Component Declaration for these design elements

-- should be placed after architecture statement but before begin keyword

-- For the following component declaration, enter RAMB16_S9_{S9 | S18 | S36},

-- RAMB16_S18_{S18 | S36}, or RAMB16_S36_S36

component RAMB16_Sm_Sn

-- synthesis translate_off

generic (

       INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INIT_A : bit_vector := X"0";

       INIT_B : bit_vector := X"0";

       INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";

       SRVAL_A : bit_vector := X"0";

       SRVAL_B : bit_vector := X"0";

       WRITE_MODE_A : string := "WRITE_FIRST";

       WRITE_MODE_B : string := "WRITE_FIRST";

);

   -- synthesis translate_on

   port (DOA : out STD_LOGIC_VECTOR (n downto 0);

         DOB : out STD_LOGIC_VECTOR (n downto 0);

         DOPA : out STD_LOGIC_VECTOR (n downto 0);

         DOPB : out STD_LOGIC_VECTOR (n downto 0);

         ADDRA : in STD_LOGIC_VECTOR (n downto 0);

         ADDRB : in STD_LOGIC_VECTOR (n downto 0);

         CLKA : in STD_ULOGIC;

         CLKB : in STD_ULOGIC;

         DIA : in STD_LOGIC_VECTOR (n downto 0);

         DIB : in STD_LOGIC_VECTOR (n downto 0);

         DIPA : in STD_LOGIC_VECTOR (n downto 0);

         DIPB : in STD_LOGIC_VECTOR (n downto 0);

         ENA: in STD_ULOGIC;

         ENB : in STD_ULOGIC;

         SSRA : in STD_ULOGIC;

         SSRB : in STD_ULOGIC;

         WEA : in STD_ULOGIC;

         WEB : in STD_ULOGIC);

end component;

-- Component Attribute Specification for design element

-- should be placed after architecture declaration

-- but before the begin keyword

-- Put attributes, if necessary

-- Component Instantiation for design element

-- Should be placed in architecture after the begin keyword

RAMB16_Sm_Sn INSTANCE_NAME : RAMB16_Sm_Sn

-- synthesis translate_off

generic map (

       INIT_00 => vector_value,

INIT_01 => vector_value,

INIT_02 => vector_value,

INIT_03 => vector_value,

INIT_04 => vector_value,

INIT_05 => vector_value,

INIT_06 => vector_value,

INIT_07 => vector_value,

INIT_08 => vector_value,

INIT_09 => vector_value,

INIT_0A => vector_value,

INIT_0B => vector_value,

INIT_0C => vector_value,

INIT_0D => vector_value,

INIT_0E => vector_value,

INIT_0F => vector_value,

INIT_10 => vector_value,

INIT_11 => vector_value,

INIT_12 => vector_value,

INIT_13 => vector_value,

INIT_14 => vector_value,

INIT_15 => vector_value,

INIT_16 => vector_value,

INIT_17 => vector_value,

INIT_18 => vector_value,

INIT_19 => vector_value,

INIT_1A => vector_value,

INIT_1B => vector_value,

INIT_1C => vector_value,

INIT_1D => vector_value,

INIT_1E => vector_value,

INIT_1F => vector_value,

INIT_20 => vector_value,

INIT_21 => vector_value,

INIT_22 => vector_value,

INIT_23 => vector_value,

INIT_24 => vector_value,

INIT_25 => vector_value,

INIT_26 => vector_value,

INIT_27 => vector_value,

INIT_28 => vector_value,

INIT_29 => vector_value,

INIT_2A => vector_value,

INIT_2B => vector_value,

INIT_2C => vector_value,

INIT_2D => vector_value,

INIT_2E => vector_value,

INIT_2F => vector_value,

INIT_30 => vector_value,

INIT_31 => vector_value,

INIT_32 => vector_value,

INIT_33 => vector_value,

INIT_34 => vector_value,

INIT_35 => vector_value,

INIT_36 => vector_value,

INIT_37 => vector_value,

INIT_38 => vector_value,

INIT_39 => vector_value,

INIT_3A => vector_value,

INIT_3B => vector_value,

INIT_3C => vector_value,

INIT_3D => vector_value,

INIT_3E => vector_value,

INIT_3F => vector_value,

       INIT_A => bit_value,

       INIT_B => bit_value,

       INITP_00 => vector_value,

       INITP_01 => vector_value,

       INITP_02 => vector_value,

       INITP_03 => vector_value,

       INITP_04 => vector_value,

       INITP_05 => vector_value,

       INITP_06 => vector_value,

       INITP_07 => vector_value,

       SRVAL_A => bit_value,

       SRVAL_B => bit_value,

       WRITE_MODE_A => string_value,

       WRITE_MODE_B => string_value)

   -- synopsys translate_on

   port map (DOA => user_DOA,

             DOB => user_DOB,

             DOPA => user_DOPA,

             DOPB => user_DOPB,

             ADDRA => user_ADDRA,

             ADDRB => user_ADDRB,

             CLKA => user_CLKA,

             CLKB => user_CLKB,

             DIA => user_DIA,

             DIB => user_DIB,

             DIPA => user_DIPA,

             DIPB => user_DIPB,

             ENA => user_ENA,

             ENB => user_ENB,

             SSRA => user_SSRA,

             SSRB => user_SSRB,

             WEA => user_WEA,

             WEB => user_WEB);

Verilog Instantiation Template for RAMB16_S9_S9, RAMB16_S9_S18, RAMB16_S9_S36, RAMB16_S18_S18, RAMB16_S18_S36, and RAMB16_S36_S36

RAMB16_Sm_Sn user_instance_name (.DOA (user_DOA),

                                 .DOB (user_DOB),

                                 .DOPA (user_DOPA),

                                 .DOPB (user_DOPB),

                                 .ADDRA (user_ADDRA),

                                 .ADDRB (user_ADDRB),

                                 .CLKA (user_CLKA),

                                 .CLKB (user_CLKB),

                                 .DIA (user_DIA),

                                 .DIB (user_DIB),

                                 .DIPA (user_DIPA),

                                 .DIPB (user_DIB),

                                 .ENA (user_ENA),

                                 .ENB (user_ENB),

                                 .SSRA (user_SSRA),

                                 .SSRB (user_SSRB),

                                 .WEA (user_WEA),

                                 .WEB (user_WEB));

    defparam user_instance_name.INIT_00 = 256_bit_hex_value;

defparam user_instance_name.INIT_01 = 256_bit_hex_value;

defparam user_instance_name.INIT_02 = 256_bit_hex_value;

defparam user_instance_name.INIT_03 = 256_bit_hex_value;

defparam user_instance_name.INIT_04 = 256_bit_hex_value;

defparam user_instance_name.INIT_05 = 256_bit_hex_value;

defparam user_instance_name.INIT_06 = 256_bit_hex_value;

defparam user_instance_name.INIT_07 = 256_bit_hex_value;

defparam user_instance_name.INIT_08 = 256_bit_hex_value;

defparam user_instance_name.INIT_09 = 256_bit_hex_value;

defparam user_instance_name.INIT_0A = 256_bit_hex_value;

defparam user_instance_name.INIT_0B = 256_bit_hex_value;

defparam user_instance_name.INIT_0C = 256_bit_hex_value;

defparam user_instance_name.INIT_0D = 256_bit_hex_value;

defparam user_instance_name.INIT_0E = 256_bit_hex_value;

defparam user_instance_name.INIT_0F = 256_bit_hex_value;

defparam user_instance_name.INIT_10 = 256_bit_hex_value;

defparam user_instance_name.INIT_11 = 256_bit_hex_value;

defparam user_instance_name.INIT_12 = 256_bit_hex_value;

defparam user_instance_name.INIT_13 = 256_bit_hex_value;

defparam user_instance_name.INIT_14 = 256_bit_hex_value;

defparam user_instance_name.INIT_15 = 256_bit_hex_value;

defparam user_instance_name.INIT_16 = 256_bit_hex_value;

defparam user_instance_name.INIT_17 = 256_bit_hex_value;

defparam user_instance_name.INIT_18 = 256_bit_hex_value;

defparam user_instance_name.INIT_19 = 256_bit_hex_value;

defparam user_instance_name.INIT_1A = 256_bit_hex_value;

defparam user_instance_name.INIT_1B = 256_bit_hex_value;

defparam user_instance_name.INIT_1C = 256_bit_hex_value;

defparam user_instance_name.INIT_1D = 256_bit_hex_value;

defparam user_instance_name.INIT_1E = 256_bit_hex_value;

defparam user_instance_name.INIT_1F = 256_bit_hex_value;

defparam user_instance_name.INIT_20 = 256_bit_hex_value;

defparam user_instance_name.INIT_21 = 256_bit_hex_value;

defparam user_instance_name.INIT_22 = 256_bit_hex_value;

defparam user_instance_name.INIT_23 = 256_bit_hex_value;

defparam user_instance_name.INIT_24 = 256_bit_hex_value;

defparam user_instance_name.INIT_25 = 256_bit_hex_value;

defparam user_instance_name.INIT_26 = 256_bit_hex_value;

defparam user_instance_name.INIT_27 = 256_bit_hex_value;

defparam user_instance_name.INIT_28 = 256_bit_hex_value;

defparam user_instance_name.INIT_29 = 256_bit_hex_value;

defparam user_instance_name.INIT_2A = 256_bit_hex_value;

defparam user_instance_name.INIT_2B = 256_bit_hex_value;

defparam user_instance_name.INIT_2C = 256_bit_hex_value;

defparam user_instance_name.INIT_2D = 256_bit_hex_value;

defparam user_instance_name.INIT_2E = 256_bit_hex_value;

defparam user_instance_name.INIT_2F = 256_bit_hex_value;

defparam user_instance_name.INIT_30 = 256_bit_hex_value;

defparam user_instance_name.INIT_31 = 256_bit_hex_value;

defparam user_instance_name.INIT_32 = 256_bit_hex_value;

defparam user_instance_name.INIT_33 = 256_bit_hex_value;

defparam user_instance_name.INIT_34 = 256_bit_hex_value;

defparam user_instance_name.INIT_35 = 256_bit_hex_value;

defparam user_instance_name.INIT_36 = 256_bit_hex_value;

defparam user_instance_name.INIT_37 = 256_bit_hex_value;

defparam user_instance_name.INIT_38 = 256_bit_hex_value;

defparam user_instance_name.INIT_39 = 256_bit_hex_value;

defparam user_instance_name.INIT_3A = 256_bit_hex_value;

defparam user_instance_name.INIT_3B = 256_bit_hex_value;

defparam user_instance_name.INIT_3C = 256_bit_hex_value;

defparam user_instance_name.INIT_3D = 256_bit_hex_value;

defparam user_instance_name.INIT_3E = 256_bit_hex_value;

defparam user_instance_name.INIT_3F = 256_bit_hex_value;

    defparam user_instance_name.INIT_A = bit_value;

    defparam user_instance_name.INIT_B = bit_value;

    defparam user_instance_name.INITP_00 = 256_bit_hex_value;

    defparam user_instance_name.INITP_01 = 256_bit_hex_value;

    defparam user_instance_name.INITP_02 = 256_bit_hex_value;

    defparam user_instance_name.INITP_03 = 256_bit_hex_value;

    defparam user_instance_name.INITP_04 = 256_bit_hex_value;

    defparam user_instance_name.INITP_05 = 256_bit_hex_value;

    defparam user_instance_name.INITP_06 = 256_bit_hex_value;

    defparam user_instance_name.INITP_07 = 256_bit_hex_value;

    defparam user_instance_name.SRVAL_A = bit_value;

    defparam user_instance_name.SRVAL_B = bit_value;

    defparam user_instance_name.WRITE_MODE_A = string_value;

    defparam user_instance_name.WRITE_MODE_B = string_value;

Commonly Used Constraints

INIT

INIT_xx

INIT_A

INIT_B

INTP_xx

SRVAL_A

SRVAL_B

WRITE_MODE_A

WRITE_MODE_B

	Port A					Port B
Component	Data Cellsa	Parity Cellsa	Address Bus	Data Bus	Parity Bus	Data Cellsa	Parity Cellsa	Address Bus	Data Bus	Parity Bus
RAMB16_S1_S1	16384 x 1	-	(13:0)	(0:0)	-	16384 x 1	-	(13:0)	(0:0)	-
RAMB16_S1_S2	16384 x 1	-	(13:0)	(0:0)	-	8192 x 2	-	(12:0)	(1:0)	-
RAMB16_S1_S4	16384 x 1	-	(13:0)	(0:0)	-	4096 x 4	-	(11:0)	(3:0)	-
RAMB16_S1_S9	16384 x 1	-	(13:0)	(0:0)	-	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)
RAMB16_S1_S18	16384 x 1	-	(13:0)	(0:0)	-	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)
RAMB16_S1_S36	16384 x 1	-	(13:0)	(0:0)	-	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)
RAMB16_S2_S2	8192 x 2	-	(12:0)	(1:0)	-	8192 x 2	-	(12:0)	(1:0)	-
RAMB16_S2_S4	8192 x 2	-	(12:0)	(1:0)	-	4096 x 4	-	(11:0)	(3:0)	-
RAMB16_S2_S9	8192 x 2	-	(12:0)	(1:0)	-	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)
RAMB16_S2_S18	8192 x 2	-	(12:0)	(1:0)	-	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)
RAMB16_S2_S36	8192 x 2	-	(12:0)	(1:0)	-	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)
RAMB16_S4_S4	4096 x 4	-	(11:0)	(3:0)	-	4096 x 4	-	(11:0)	(3:0)	-
RAMB16_S4_S9	4096 x 4	-	(11:0)	(3:0)	-	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)
RAMB16_S4_S18	4096 x 4	-	(11:0)	(3:0)	-	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)
RAMB16_S4_S36	4096 x 4	-	(11:0)	(3:0)	-	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)
RAMB16_S9_S9	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)
RAMB16_S9_S18	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)
RAMB16_S9_S36	2048 x 8	2048 x 1	(10:0)	(7:0)	(0:0)	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)
RAMB16_S18_S18	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)
RAMB16_S18_S36	1024 x 16	1024 x 2	(9:0)	(15:0)	(1:0)	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)
RAMB16_S36_S36	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)	512 x 32	512 x 4	(8:0)	(31:0)	(3:0)
aDepth x Width

Inputs								Outputs
GSR	ENA	SSRA	WEA	CLKA	ADDRA	DIA	DIPA	DOA	DOPA	RAM Contents
										Data RAM	Parity RAM
1	X	X	X	X	X	X	X	INIT_A	INIT_A	No Chg	No Chg
0	0	X	X	X	X	X	X	No Chg	No Chg	No Chg	No Chg
0	1	1	0		X	X	X	SRVAL_A	SRVAL_A	No Chg	No Chg
0	1	1	1		addr	data	pdata	SRVAL_A	SRVAL_A	RAM(addr) =>data	RAM(addr) =>pdata
0	1	0	0		addr	X	X	RAM(addr)	RAM(addr)	No Chg	No Chg
0	1	0	1		addr	data	pdata	No Chg1 RAM (addr)2 data3	No Chg1 RAM(addr)2 pdata3	RAM(addr) =>data	RAM(addr) =>pdata
GSR=Global Set Reset INIT_A=Value specified by the INIT_A attribute for output register. Default is all zeros. SRVAL_A=register value addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data pdata=RAM parity data 1WRITE_MODE_A=NO_CHANGE 2WRITE_MODE_A=READ_FIRST 3WRITE_MODE_A=WRITE_FIRST

Inputs								Outputs
GSR	ENB	SSRB	WEB	CLKB	ADDRB	DIB	DIPB	DOB	DOPB	RAM Contents
										Data RAM	Parity RAM
1	X	X	X	X	X	X	X	INIT_B	INIT_B	No Chg	No Chg
0	0	X	X	X	X	X	X	No Chg	No Chg	No Chg	No Chg
0	1	1	0		X	X	X	SRVAL_B	SRVAL_B	No Chg	No Chg
0	1	1	1		addr	data	pdata	SRVAL_B	SRVAL_B	RAM(addr) =>data	RAM(addr) =>pdata
0	1	0	0		addr	X	X	RAM(addr)	RAM(addr)	No Chg	No Chg
0	1	0	1		addr	data	pdata	No Chg1 RAM (addr)2 data3	No Chg1 RAM(addr)2 pdata3	RAM(addr) =>data	RAM(addr) =>pdata
GSR=Global Set Reset INIT_B=Value specified by the INIT_B attribute for output registers. Default is all zeros. SRVAL_B=register value addr=RAM address RAM(addr)=RAM contents at address ADDR data=RAM input data pdata=RAM parity data 1WRITE_MODE_B=NO_CHANGE 2WRITE_MODE_B=READ_FIRST 3WRITE_MODE_B=WRITE_FIRST

DataWidth	Port Data Addresses
1	16384	<--	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	09	08	07	06	05	04	03	02	01	00
2	8192	<--	15		14		13		12		11		10		09		08		07		06		05		04		03		02		01		00
4	4096	<--	07				06				05				04				03				02				01				00
8	2048	<--	03								02								01								00
16	1024	<--	01																00
32	512	<--	00