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Example 2: How to Synthesize Verilog Designs Using Command Line Mode

The goal of this example is to synthesize a hierarchical Verilog design for a Virtex FPGA using Command Line Mode.

Two main cases are considered:

  • All design blocks (modules) are located in a single Verilog file.
  • Each design block (module) is located in a separate Verilog file.

Example 2 uses a Verilog design, called watchver. These files can be found in the ISEexamples\watchver directory of the ISE installation directory.

  • stopwatch.v
  • statmach.v
  • decode.v
  • cnt60.v
  • smallcntr.v
  • hex2led.v

This design contains seven modules:

  • stopwatch
  • statmach
  • tenths (a CORE Generator core)
  • decode
  • cnt60
  • smallcntr
  • HEX2LED

Case 1: All Design Blocks in a Single File

All design blocks will be located in a single Verilog file.

  1. Create a new directory called vlg_s.
  2. Copy the following files from the ISEexamples\watchver directory of the ISE installation directory to the newly created vlg_s directory.
  3. Copy and paste the contents of the files into a single file called 'watchver.ver'. Make sure the contents of 'stopwatch.v' appear last in the file.

To synthesize this design for Speed with optimization effort 1 (Low), execute the following command:

run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1

Note All options in this command except -opt_mode and -opt_level are mandatory. Default values are used for all other options.

This command can be launched in two ways:

  • Directly from the XST shell
  • Script mode

XST Shell

To use the XST shell, perform the following steps.

  1. In the tcsh or other shell, enter xst. XST starts and prompts you with the following message:
Release 5.1i - XST F.23
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
-->
  1. Enter the following command at the - -> prompt to start synthesis:

    2. run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6
    -opt_mode Speed -opt_level 1

  2. When the synthesis is complete and XST displays the - -> prompt. Enter quit to exit the XST shell.

During this run, XST creates the watchver.ngc file. This is an NGC file ready for the implementation tools.

Note All messages issued by XST are displayed on the screen only. If you want to save your messages in a separate log file, then the best way is to use script mode to launch XST.

In the previous run, XST synthesized the module stopwatch, as the top level module of the design. XST automatically recognizes the hierarchy and detects the top level module. If you would like to synthesize just HEX2LED and check its performance independently of the other blocks, you can specify the top level module to synthesize in the command line, using the -top option (please refer to )

run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1 -top HEX2LED

Script Mode

It can be very tedious work entering XST commands directly into the XST shell, especially when you have to specify several options and execute the same command several times. You can run XST in a script mode as follows.

  1. Open a new file called xst.scr in the current directory. Put the previously executed XST shell command into this file and save it.

    2. run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6
    -opt_mode Speed -opt_level 1

  2. From the tcsh or other shell, enter the following command to start synthesis.

    3. xst -ifn xst.scr

During this run, XST creates the following files:

  • watchvhd.ngc: an NGC file ready for the implementation tools
  • xst.srp: the xst script log file

You can improve the readability of the xst.scr file, especially if you use many options to run synthesis. You can place each option with its value on a separate line, respecting the following rules:

  • The first line must contain only the run command without any options.
  • There must be no empty lines in the middle of the command
  • Each line (except the first one) must start with a dash (-)

For the previously used command, you may have the xst.cmd file in the following form:

run
-ifn watchver.v
-ifmt Verilog
-ofn watchver.ngc
-ofmt NGC
-p xcv50-bg256-6
-opt_mode Speed
-opt_level 1

Case 2

Each design block is located in a separate Verilog file.

  1. Create a new directory named vlg_m.
  2. Copy the watchver design files from the ISEexamples\watchver directory of the ISE installation directory to the newly created vlg_m directory.

To synthesize the design, which is now represented by four Verilog files, you can use the project approach supported in XST. A Verilog project file contains a set of "include" Verilog statements (one each per Verilog module). The order of the files in the project is not important. XST is able to recognize the hierarchy and compile Verilog files in the correct order. Moreover, XST automatically detects the top level module for synthesis.

For our example:

  1. Open a new file, called watchver.v.
  2. Enter the names of the Verilog files into this file in any order and save it:
    `include "decode.v"
    `include "statmach.v"
    `include "stopwatch.v"
    `include "cnt60.v"
    `include "smallcntr.v"
    `include "hex2led.v"
  1. To synthesize the design, execute the following command from the XST shell or via a script file:

    2. run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc -ofmt NGC -p xcv50-bg256-6
    -opt_mode Speed -opt_level 1

If you want to synthesize just HEX2LED and check its performance independently of the other blocks, you can specify the top level module to synthesize in the command line, using the -top option (please refer to for more information):

run -ifn watchver.v -ifmt Verilog -ofn watchver.ngc
-ofmt NGC -p xcv50-bg256-6 -opt_mode Speed
-opt_level 1 -top HEX2LED

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