The Device Architecture window displays the die for a selected part type. This window is a scrollable, scalable view of a resource map of the device that is specified in your design. You floorplan by dragging selected global logic or hierarchical logic groups from the Design Hierarchy window and dropping it into this window.
The Device Architecture window includes the following features:
Displays a view of the spatial layout of your design logic as area constraints in terms of the resource requirements of that logic.
Includes a grid representing the CLB/slice coordinate system used for your target device.
Displays a resource map for your target device, including I/O pins, CLB/slice tiles, global buffers, block RAM columns, processors, and so on. The various layout views are superimposed on this resource map and grid to provide a common spatial reference for the data.
Allows you to control design placement by associating items in the Design Hierarchy or Design Object List window with resources in the map through location and area constraints.
Allows you to select area constraints, resize them, move them in the Device Architecture view, and drag and drop I/Os and global logic into the Device Architecture view.
Allows you to create non-rectangular areas by adding rectangles to the existing area constraint.
The Device Architecture window shows an abstract view of the resources available for your target device. Internal logic resources are represented as a grid of "tiles", each tile representing a CLB or slice in the device. The specific logical elements in these tiles are a function of the device architecture. For example, Virtex devices are represented with CLB tiles, each composed of 4 LUTs, 4 Registers, 4 carry multiplexers, 2 BUFTs, and miscellaneous logic gates. In addition, the Device Architecture window shows abstract representations of I/O logic, and specific global logic such as clock buffers, block RAM, and so forth.
In the Device Architecture window you can control the display of I/O banks and differential I/O pairs as follows:
Select Preferences from the Edit menu to display the Preferences dialog box.
Select the Resources tab.
To change the display, select the Show I/O Banks and Show Differential I/O Pairs options.
Note Alternatively, you can use the Show Differential Pairs and Show I/O Banks commands in the IOBs menu.
Select Close.
You can designate resources or CLB/slice tiles in the Device Architecture window as prohibited or not prohibited. Prohibited resources appear as gray sites or regions in the window. You can use the Prohibit Mode and Allow Mode commands from the PACE toolbar or select these commands from the Tools menu. You can also prohibit pins in the Package Pins window.
Area constraints associated with nodes of your design hierarchy are displayed as rectangles. Optionally, the rectangles can overlap providing the overlap does not leave a deficit of resources for the constrained logic. When you select an area, sizing handles appear at each corner and the center of each side. You can use these handles to resize the area with the mouse. You can add a rectangle to an area to change it to a non-rectangular area.
See Area Padding for more information.
Ratsnests show the connectivity between logic in the layout. Ratsnest lines connected to area rectangles generally end near the center of the area. By default, the ratsnest display is turned On. The ratsnest lines can be turned on or off.