The Design Object List window displays elements contained in hierarchies and groups selected in the Design Hierarchy window.
Elements are displayed in columns representing element type, color information, and sub-item information. Clicking on a column header sorts the list using that column's data as criteria. The DOL provides drag and drop support for easy element manipulation. There are three implementations of the DOL corresponding to the three root hierarchies in the Design Hierarchy:
The DOL window displays individual logic elements (I/Os) as well as groups (groups are displayed in the bottom part of the window).
Some of the columnar data is shown as empty and uneditable when groups are displayed in the list. For example, the direction is displayed for groups only if all of the I/Os in the group have the same direction.
I/Os are displayed with their full hierarchical name.
When a group is selected, the DOL selects all the I/O Pins that belong to that group.
The DOL contains the following columns: Color, I/O Name, I/O Direction, Location, I/O Bank, I/O Standard.
I/O Direction is obtained from the NGD file. Possible values are input, output, inout, and undefined.
Location information is entered by you or read from a UCF. Possible values are legal IOB pin names, bank constraints, and edge constraints.
Bank/edge information is obtained from the I/O location entered by you. Possible values for Banks BANK0-BANK7. Possible values for Edges and Half-edges are TOP (T), LEFT (L), BOTTOM (B), RIGHT (R), TOP-LEFT (TL), BOTTOM-RIGHT (BR), LEFT-TOP (LT), RIGHT-TOP (RT), TOP-RIGHT (TR), LEFT-BOTTOM (LB), BOTTOM-LEFT (BL), AND RIGHT-BOTTOM (RB).
Note This field is read-only and is only visible when a specific location constraint has been applied.
IOSTANDARD information is obtained from the NGD file or can be selected by you. Possible values depend on the device family; examples are LVTTL, GTL, and LVCMOS25. If no standard is specified for a pin, it uses the default standard for that device.
I/Os that are part of a differential pair are handled together. When the positive pin is placed in a legal location, the complementary pin is automatically placed.
Changing a group's columnar data changes the data in that column for all the I/Os contained in that group.
I/Os and Groups can be dragged into and out of the list for the following purposes:
Out: Placing I/Os in the Package Pin or Device Architecture window
In: Removing I/Os from the Package Pin or Device Architecture window
Drag and drop is supported from the Design Hierarchy as well
You can change colors by selecting the I/Os and selecting the required color button in the Color toolbar
The DOL displays your design's global logic symbols (GT, DCM, BRAM, MULT, PPC405, DLL, or BUFG.)
Contains these columns: Symbol Name, Symbol Type, Location and Color.
Does not display contained hierarchies because the global logic does not contain hierarchies.
The DOL displays your design's logic hierarchies.
Note The DOL only displays hierarchies, and does not display individual logic symbols.
Contains these columns: Hierarchy Name, Symbol Count, and Color.