VHDL

VHDL

In VHDL code, constraints can be described with VHDL attributes. Before it can be used, a constraint must be declared with the following syntax:

attribute attribute_name : string;

Example:

attribute RLOC : string;

An attribute can be declared in an entity or architecture. If declared in the entity, it is visible both in the entity and the architecture body. If the attribute is declared in the architecture, it cannot be used in the entity declaration. Once declared you can specify a VHDL attribute as follows:

attribute attribute_name of {component_name|label_name|entity_name|signal_name
|variable_name|type_name}: {component|label|entity|signal
|variable|type} is attribute_value;

Accepted attribute_values depend on the attribute type.

Examples:

attribute RLOC of u123 : label is "R11C1.S0";

attribute bufg of my_clock: signal is “clk”;

For Xilinx, the most common objects are signal, entity, and label. A label describes an instance of a component.

VHDL is case insensitive.

For a list of supported constraints, see “Constraint Entry Table”.