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DESKEW_ADJUST
DESKEW_ADJUST Description
This constraint sets configuration bits affecting the clock delay alignment between the DCM output clocks and an FPGA clock input pin. The attribute value should be selected solely based on the type of clocking arrangement used in the customer design, most commonly either SOURCE_SYNCHRONOUS or SYSTEM_SYNCHRONOUS (default).
The clock delay alignment is taken into account in the Tdcmino delay value in the timing report. Tdcmino will be a larger number (i.e., less negative, since Tdcmino is typically negative) when using the SOURCE_SYNCHRONOUS value with the end result of a longer clock delay to the IOB clock input. This will affect the setup and hold times by reducing the input setup time and increasing the input hold time. The overall data sample window is smaller with SOURCE_SYNCHRONOUS due to the smaller variance in the clock delay through the DCM.
This constraint should not be used to achieve phase shift on DCM clock outputs. Instead, use the CLKOUT_PHASE_SHIFT and PHASE_SHIFT constraints to achieve accurate phase shifting.
DESKEW_ADJUST Architecture Support
The following table indicates supported and unsupported architectures.
DESKEW_ADJUST Applicable Elements
DCM
DESKEW_ADJUST Propagation Rules
It is illegal to attach DESKEW_ADJUST to a net or signal. When attached to a DCM, the DESKEW_ADJUST constraint is propagated to all applicable elements of the DCM.
DESKEW_ADJUST Syntax Examples
ECS Schematic Editor
Not applicable.
VHDL
Before using DESKEW_ADJUST, declare it with the following syntax:
attribute deskew_adjust: string;
After DESKEW_ADJUST has been declared, specify the VHDL constraint as follows:
attribute deskew_adjust of dcm_instance_name : label is “{SYSTEM_SYNCHRONOUS|SOURCE_SYNCHRONOUS}”;
SYSTEM_SYNCHRONOUS is the default.
For a more detailed discussion of the basic VHDL syntax, see “VHDL”.
Verilog
Specify as follows:
// synthesis attribute deskew_adjust [of] dcm_instance_name [is] {SYSTEM_SYNCHRONOUS|SOURCE_SYNCHRONOUS};
SYSTEM_SYNCHRONOUS is the default.
For a more detailed discussion of the basic Verilog syntax, see “Verilog”.
ABEL
Not applicable.
UCF/NCF
INST “foo/bar” DESKEW_ADJUST=SYSTEM_SYNCHRONOUS;
Constraints Editor
Not applicable.
PCF
Not applicable.
XCF
Not applicable.
Floorplanner
Not applicable.
PACE
Not applicable.
FPGA Editor
Not applicable.
XST Command Line
Not applicable.
Project Navigator
Not applicable.
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