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DFS_FREQUENCY_MODE
DFS_FREQUENCY_MODE Description
DFS_FREQUENCY_MODE is an advanced DCM constraint. It specifies the frequency range allowed at the CLKIN input and at the output clocks for the DCM’s digital frequency synthesizer (DFS).
DFS_FREQUENCY_MODE Architecture Support
The following table indicates supported and unsupported architectures.
DFS_FREQUENCY_MODE Applicable Elements
DCM (Digital Clock Manager)
DFS_FREQUENCY_MODE Propagation Rules
It is illegal to attach DFS_FREQUENCY_MODE to a net or signal. When attached to a DCM, DFS_FREQUENCY_MODE is propagated to all applicable elements of the DCM.
DFS_FREQUENCY_MODE Syntax Examples
ECS Schematic Editor
Attach to a DCM instance.
Attribute Name—DFS_FREQUENCY_MODE
Attribute Values—LOW, HIGH
VHDL
Before using DFS_FREQUENCY_MODE, declare it with the following syntax:
attribute dfs_frequency_mode: string;
After DFS_FREQUENCY_MODE has been declared, specify the VHDL constraint as follows:
attribute dfs_frequency_mode of {component_name|label_name}: {component|label} is “{HIGH|LOW}”;
For a more detailed discussion of the basic VHDL syntax, see “VHDL”.
Verilog
Specify as follows:
// synthesis attribute dfs_frequency_mode [of] {module_name|instance_name} [is] {HIGH|LOW};
For a more detailed discussion of the basic Verilog syntax, see “Verilog”.
ABEL
Not applicable.
UCF/NCF
The basic UCF syntax is:
INST “instance_name” DFS_FREQUENCY_MODE={LOW|HIGH};
where
- LOW, the default, specifies that the frequency of the clock signal at the CLKIN input and at the DFS output clocks (CLKFX and CLKFX180) must fall within the Low frequency range. See the The Programmable Logic Data Book for the current Low frequency range values for the input clocks (DFS_CLKIN_MIN_LF and DFS_CLKIN_MAX_LF) and for the output clocks (DFS_CLKOUT_MIN_LF and DFS_CLKOUT_MAX_LF).
- HIGH specifies that the frequency of the clock signal at the CLKIN input and at the DFS output clocks (CLKFX and CLKFX180) must fall within the High frequency range. See the The Programmable Logic Data Book for the current High frequency range values for the input clocks (DFS_CLKIN_MIN_HF and DFS_CLKIN_MAX_HF) and for the output clocks (DFS_CLKOUT_MIN_HF and DFS_CLKOUT_MAX_HF).
The following statement limits the frequency of the clock signal at the CLKIN input and at the DFS output clocks to the High frequency range.
INST “foo/bar” DFS_FREQUENCY_MODE=HIGH;
XCF
Not applicable.
Constraints Editor
Not applicable.
PCF
Not applicable.
Floorplanner
Not applicable.
PACE
Not applicable.
FPGA Editor
Not applicable.
XST Command Line
Not applicable.
Project Navigator
Not applicable.
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