ORCY

OR with Carry Logic

Architectures Supported
ORCY
Spartan-II, Spartan-IIE	No
Spartan-3	No
Virtex, Virtex-E	No
Virtex-II, Virtex-II Pro, Virtex-II Pro X	Primitive
XC9500, XC9500XV, XC9500XL	No
CoolRunner XPLA3	No
CoolRunner-II	No

ORCY is a special OR with general O output used for generating faster and smaller arithmetic functions.

Each Virtex-II, Virtex-II Pro, and Virtex-II Pro X slice contains a dedicated 2-input OR gate that ORs together carry out values for a series of horizontally adjacent carry chains. The OR gate gets one input external to the slice and the other input from the output of the high order carry mux. The OR gate's output drives the next slice's OR gate horizontally across the die.

Only MUXCY outputs can drive the signal on the CI pin. Only ORCY outputs or logic zero can drive the I pin.

Usage

For HDL, the ORCY design element should be instantiated rather than inferred.

VHDL Instantiation Template


-- Component Declaration for ORCY should be placed 
-- after architecture statement but before begin keyword 

component ORCY
   port (O : out STD_ULOGIC;
         CI : in STD_ULOGIC;
         I : in STD_ULOGIC);
end component;

-- Component Attribute specification for ORCY
-- should be placed after architecture declaration but 
-- before the begin keyword 

-- Enter attributes here 


-- Component Instantiation for ORCY should be placed 
-- in architecture after the begin keyword 

ORCY_INSTANCE_NAME : ORCY
      port map (O => user_O,
                CI => user_CI,

                I => user_I);

Verilog Instantiation Template


ORCY instance_name (.O (user_O),
                    .CI (user_CI),

                    .I (user_I));